ADSP-BF504BCPZ-4 Analog Devices Inc, ADSP-BF504BCPZ-4 Datasheet - Page 9

• Manufacturer Part Number: ADSP-BF504BCPZ-4
• Description: Low Cost Blackfin Wtih Processor Only
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF504BCPZ-4

• Interface: CAN, EBI/EMI, I²C, IrDA, PPI, SPI, SPORT, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 68kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.29V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FLASH MEMORY
The ADSP-BF504F and ADSP-BF506F processors include an
on-chip 32M bit (×16, multiple bank, burst) Flash memory. The
features of this memory include:
Flash memory ships from the factory in an erased state except
for block 0 of the parameter bank. Block 0 of the Flash memory
parameter bank ships from the factory in an unknown state. An
erase operation should be performed prior to programming this
block.
DMA CONTROLLERS
The processor has multiple, independent DMA channels that
support automated data transfers with minimal overhead for
the processor core. DMA transfers can occur between the pro-
cessor’s internal memories and any of its DMA-capable
peripherals. Additionally, DMA transfers can be accomplished
between any of the DMA-capable peripherals and external
devices connected to the external memory interface. DMA-
capable peripherals include the SPORTs, SPI ports, UARTs,
RSI, and PPI. Each individual DMA-capable peripheral has at
least one dedicated DMA channel.
The processor DMA controller supports both one-dimensional
(1-D) and two-dimensional (2-D) DMA transfers. DMA trans-
fer initialization can be implemented from registers or from sets
of parameters called descriptor blocks.
The 2-D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to ±32K elements. Furthermore, the
column step size can be less than the row step size, allowing
• Synchronous/asynchronous read
• Synchronous burst read suspend
• Memory blocks
• Dual operations
• Block locking
• Security
• Common Flash interface (CFI)
• 100,000 program/erase cycles per block
• Synchronous burst read mode: 50 MHz
• Asynchronous/synchronous read mode
• Random access times: 70 ns
• Multiple bank memory array: 4M bit banks
• Parameter blocks (top location)
• Program erase in one bank while read in others
• No delay between read and write operations
• All blocks locked at power-up
• Any combination of blocks can be locked or locked
• 128-bit user programmable OTP cells
• 64-bit unique device number
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Rev. 0 | Page 9 of 80 | December 2010
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be de-
interleaved on the fly.
Examples of DMA types supported by the processor DMA con-
troller include:
In addition to the dedicated peripheral DMA channels, there are
two memory DMA channels, which are provided for transfers
between the various memories of the processor system with
minimal processor intervention. Memory DMA transfers can be
controlled by a very flexible descriptor-based methodology or
by a standard register-based autobuffer mechanism.
WATCHDOG TIMER
The processor includes a 32-bit timer that can be used to imple-
ment a software watchdog function. A software watchdog can
improve system availability by forcing the processor to a known
state through generation of a core and system reset, nonmask-
able interrupt (NMI), or general-purpose interrupt, if the timer
expires before being reset by software. The programmer initial-
izes the count value of the timer, enables the appropriate
interrupt, then enables the timer. Thereafter, the software must
reload the counter before it counts to zero from the pro-
grammed value. This protects the system from remaining in an
unknown state where software, which would normally reset the
timer, has stopped running due to an external noise condition
or software error.
If configured to generate a reset, the watchdog timer resets both
the core and the processor peripherals. After a reset, software
can determine whether the watchdog was the source of the
hardware reset by interrogating a status bit in the watchdog
timer control register.
The timer is clocked by the system clock (SCLK) at a maximum
frequency of f
TIMERS
There are nine general-purpose programmable timer units in
the processors. Eight timers have an external pin that can be
configured either as a pulse width modulator (PWM) or timer
output, as an input to clock the timer, or as a mechanism for
measuring pulse widths and periods of external events. These
timers can be synchronized to an external clock input to the sev-
eral other associated PF pins, to an external clock input to the
PPI_CLK input pin, or to the internal SCLK.
The timer units can be used in conjunction with the two UARTs
to measure the width of the pulses in the data stream to provide
a software auto-baud detect function for the respective serial
channels.
• A single, linear buffer that stops upon completion
• A circular, auto-refreshing buffer that interrupts on each
• 1-D or 2-D DMA using a linked list of descriptors
• 2-D DMA using an array of descriptors, specifying only the
full or fractionally full buffer
base DMA address within a common page
SCLK
.