ADSP-BF504BCPZ-4 Analog Devices Inc, ADSP-BF504BCPZ-4 Datasheet - Page 51

• Manufacturer Part Number: ADSP-BF504BCPZ-4
• Description: Low Cost Blackfin Wtih Processor Only
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF504BCPZ-4

• Interface: CAN, EBI/EMI, I²C, IrDA, PPI, SPI, SPORT, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 68kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.29V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Output Disable Time Measurement
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The output disable time t
difference between t
of
The time for the voltage on the bus to decay by V is dependent
on the capacitive load C
can be approximated by the equation:
The time t
0.15 V for V
The time t
nal switches, to when the output voltage decays V from the
measured output high or output low voltage.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
to be the difference between the processor’s output voltage and
the input threshold for the device requiring the hold time. C
the total bus capacitance (per data line), and I
age or three-state current (per data line). The hold time will be
t
Processor—Timing Specifications on Page
Capacitive Loading
Output delays and holds are based on standard capacitive loads
of an average of 6 pF on all pins (see
to (V
how output rise time varies with capacitance. The delay and
hold specifications given should be derated by a factor derived
from these figures. The graphs in these figures may not be linear
outside the ranges shown.
DECAY
V
V equal to 0.25 V for V
LOAD
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD), IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
Figure
4pF
plus the various output disable times as specified in the
DDEXT
50:
Figure 43. Equivalent Device Loading for AC Measurements
42.
DECAY
DIS
) /2. The graphs of
_
DDEXT
MEASURED
t
DIS
70:
50:
400:
2pF
DECAY
is calculated with test loads C
(nominal) = 1.8 V.
=
using the equation given above. Choose V
is the interval from when the reference sig-
DIS
t
DECAY
t
_
DIS_MEASURED
MEASURED
L
(Includes All Fixtures)
and the load current I
DDEXT
45:
0.5pF
=
(nominal) = 2.5 V/3.3 V and
and t
Figure 44
C
TESTER PIN ELECTRONICS
DECAY
L
ZO = 50: (impedance)
TD = 4.04 r 1.18 ns
Figure
–
V
t
as shown on the left side
through
DECAY
I
T1
L
32.
43). V
L
and I
L
L
is the total leak-
. This decay time
Figure 49
Rev. 0 | Page 51 of 80 | December 2010
LOAD
L
, and with
DIS
OUTPUT
is equal
is the
DUT
show
L
is
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
Figure 44. Driver Type B Typical Rise and Fall Times (10%–90%) vs.
Figure 45. Driver Type B Typical Rise and Fall Times (10%–90%) vs.
Figure 46. Driver Type B Typical Rise and Fall Times (10%–90%) vs.
9
8
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
50
50
50
Load Capacitance (1.8 V V
Load Capacitance (2.5 V V
Load Capacitance (3.3 V V
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
100
100
100
t
RISE
150
150
DDEXT
DDEXT
DDEXT
150
t
t
RISE
RISE
)
)
)
t
t
t
t
t
FALL
t
t
RISE
FALL
RISE
FALL
RISE
FALL
t
FALL
= 1.8V @ 25
= 3.3V @ 25
= 1.8V @ 25
= 3.3V @ 25
= 2.5V @ 25
= 2.5V @ 25
t
FALL
200
200
200
° C
° C
° C
° C
° C
° C
250
250
250