ADSP-BF504BCPZ-4 Analog Devices Inc, ADSP-BF504BCPZ-4 Datasheet - Page 22

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ADSP-BF504BCPZ-4

Manufacturer Part Number
ADSP-BF504BCPZ-4
Description
Low Cost Blackfin Wtih Processor Only
Manufacturer
Analog Devices Inc
Series
Blackfin®r
Type
Fixed Pointr
Datasheet

Specifications of ADSP-BF504BCPZ-4

Interface
CAN, EBI/EMI, I²C, IrDA, PPI, SPI, SPORT, UART/USART
Clock Rate
400MHz
Non-volatile Memory
External
On-chip Ram
68kB
Voltage - I/o
1.8V, 2.5V, 3.3V
Voltage - Core
1.29V
Operating Temperature
-40°C ~ 85°C
Mounting Type
*
Package / Case
*
Rohs Compliant
YES
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADSP-BF504BCPZ-4F
Manufacturer:
TI
Quantity:
1 000
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
Table 11. Processor—Signal Descriptions (Continued)
Signal Name
Port H: GPIO and Multiplexed Peripherals
TWI (2-Wire Interface) Port
JTAG Port
Clock
Mode Controls
ADSP-BF50x Voltage Regulation I/F
Power Supplies
PG14/UA0_RTS/SD_D6/TMR0/PPI_FS1/CUD1
PG15/UA0_CTS/SD_D7/TMR1/PPI_FS2/CDG1
PH0/ACM_A2/DT1PRI/SPI0_SEL3/WAKEUP
PH1/ACM_A1/TFS1/SPI1_SEL3/TACLK3
PH2/ACM_A0/TSCLK1/SPI1_SEL2/TACI7
SCL
SDA
TCK
TDO
TDI
TMS
TRST
EMU
CLKIN
XTAL
EXTCLK
RESET
NMI
BMODE2–0
EXT_WAKE
PG
V
V
V
GND
DDEXT
DDINT
DDFLASH
I/O
5 V
I/O
5 V
Type Function
Rev. 0 | Page 22 of 80 | December 2010
I/O GPIO/UART0 RTS/SD Data 6/Timer0/PPI FS1/Count Up Dir 1
I/O GPIO/UART0 CTS/SD Data 7/Timer1/PPI FS2/Count Down Dir 1
I/O GPIO/ADC CM A2/SPORT1 TX Pri Data/SPI0 Slave Select 3/Wake-up Input
I/O GPIO/ADC CM A1/SPORT1 TX Frame Sync/SPI1 Slave Select 3/Alt Timer CLK 3
I/O GPIO/ADC CM A0/SPORT1 TX Serial CLK/SPI1 Slave Select 2/Alt Capture In 7
O
O
O
O
O
G
P
P
P
I
I
I
I
I
I
I
I
I
TWI Serial Clock (This signal is an open-drain output and requires a pull-up
resistor. Consult version 2.1 of the I
value.)
TWI Serial Data (This signal is an open-drain output and requires a pull-up
resistor. Consult version 2.1 of the I
value.)
JTAG CLK
JTAG Serial Data Out
JTAG Serial Data In
JTAG Mode Select
JTAG Reset
(This signal should be pulled low if the JTAG port is not used.)
Emulation Output
CLK/Crystal In
Crystal Output
Clock Output
Reset
Nonmaskable Interrupt
(This signal should be pulled high when not used.)
Boot Mode Strap 2-0
Wake up Indication
Power Good
ALL SUPPLIES MUST BE POWERED
See
I/O Power Supply
Internal Power Supply
Flash Memory Power Supply
Ground for All Supplies
Processor—Operating Conditions on Page
2
2
C specification for the proper resistor
C specification for the proper resistor
25.
Driver
Type
D
D
C
C
C
C
C
C
C
B
C

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