ADSP-BF504BCPZ-4 Analog Devices Inc, ADSP-BF504BCPZ-4 Datasheet - Page 61

• Manufacturer Part Number: ADSP-BF504BCPZ-4
• Description: Low Cost Blackfin Wtih Processor Only
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF504BCPZ-4

• Interface: CAN, EBI/EMI, I²C, IrDA, PPI, SPI, SPORT, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 68kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.29V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Intermodulation Distortion (IMD)
Common-Mode Rejection Ratio (CMRR)
Power Supply Rejection Ratio (PSRR)
Thermal Hysteresis
determining how much that signal is attenuated in the
selected channel with a 50 kHz signal (0 V to V
obtained is the worst-case across all 12 channels for the ADC.
With inputs consisting of sine waves at two frequencies, fa
and fb, any active device with non-linearities create distortion
products at sum, and difference frequencies of mfa ± nfb
where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion
terms are those for which neither m nor n are equal to zero.
For example, the second-order terms include (fa + fb) and
(fa fb), while the third-order terms include (2fa + fb),
(2fa fb), (fa + 2fb), and (fa 2fb).
The ADC is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second-order terms are usually distanced in
frequency from the original sine waves, while the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second-order and third-order terms are speci-
fied separately. The calculation of the inter-modulation
distortion is as per the THD specification, where it is the ratio
of the rms sum of the individual distortion products to the
rms amplitude of the sum of the fundamentals expressed in
dBs.
CMRR is defined as the ratio of the power in the ADC output
at full-scale frequency, f, to the power of a 100 mV p-p sine
wave applied to the common-mode voltage of V
frequency f
where:
Pf is the power at frequency f in the ADC output.
Pf
Variations in power supply affect the full-scale transition but
not the converter’s linearity. PSRR is the maximum change in
the full-scale transition point due to a change in power supply
voltage from the nominal value (see
ply Ripple Frequency Without Supply
Thermal hysteresis is defined as the absolute maximum
change of reference output voltage (V
cycled through temperature from either:
or
It is expressed in ppm by:
S
is the power at frequency f
CMRR (dB) = 10 log(Pf/Pf
T_HYS+ = +25°C to T
T_HYS = +25°C to T
V
HYS
(
S
ppm
as:
)
V
REF
(
25
MIN
MAX
V
) C
to +25°C
S
REF
in the ADC output.
S
to +25°C
)
(
V
25
REF
Figure 50 (PSRR vs. Sup-
) C
REF
(
Decoupling).
T
) after the device is
_
HYS
REF
)
Rev. 0 | Page 61 of 80 | December 2010
IN+
). The result
10
and V
6
IN
of
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
ADC—THEORY OF OPERATION
The following sections describe the ADC theory of operation.
Circuit Information
The ADC is a fast, micropower, dual, 12-bit, single-supply,
ADC that operates from a 2.7 V to a 5.25 V supply. When oper-
ated from a 5 V supply, the ADC is capable of throughput rates
of up to 2 MSPS when provided with a 32 MHz clock, and a
throughput rate of up to 1.5 MSPS at 3 V.
The ADC contains two on-chip, differential track-and-hold
amplifiers, two successive approximation ADCs, and a serial
interface with two separate data output pins.
The serial clock input accesses data from the part but also pro-
vides the clock source for each successive approximation ADC.
The analog input range for the part can be selected to be a 0 V to
V
ended or differential analog inputs. The ADC has an on-chip
2.5 V reference that can be overdriven when an external refer-
ence is preferred. If the internal reference is to be used elsewhere
in a system, then the output needs to buffered first.
The ADC also features power-down options to allow power sav-
ing between conversions. The power-down feature is
implemented via the standard serial interface, as described in
the
Converter Operation
The ADC has two successive approximation ADCs, each based
around two capacitive DACs.
Phase) and
schematics of one of these ADCs in acquisition and conversion
phase, respectively. The ADC is comprised of control logic, a
SAR, and two capacitive DACs. In
Phase) (the acquisition phase), SW3 is closed, SW1 and SW2 are
in Position A, the comparator is held in a balanced condition,
and the sampling capacitor arrays acquire the differential signal
on the input.
REF
where:
ADC—Modes of Operation
input or a 2 × V
V
V
T_HYS+ or T_HYS.
V
V
IN+
IN–
REF
REF
Figure 63 (ADC Conversion
(25°C) is V
(T_HYS) is the maximum change of V
B
A
A
B
V
REF
SW1
SW2
Figure 62. ADC Acquisition Phase
REF
C
C
S
S
REF
input, configured with either single-
at 25°C.
Figure 62 (ADC Acquisition
SW3
section.
COMPARATOR
Figure 62 (ADC Acquisition
Phase) show simplified
CAPACITIVE
CAPACITIVE
CONTROL
DAC
LOGIC
DAC
REF
at