EP2SGX90EF1152I4N Altera, EP2SGX90EF1152I4N Datasheet - Page 138

• Manufacturer Part Number: EP2SGX90EF1152I4N
• Description: Stratix II GX
• Manufacturer: Altera

Specifications of EP2SGX90EF1152I4N

• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / Rohs Status: Compliant

I/O Structure
2–130
Stratix II GX Device Handbook, Volume 1
Series termination without
calibration
Table 2–34. On-Chip Termination Support by I/O Banks (Part 1 of 2)
On-Chip Termination Support
On-Chip Termination
Stratix II GX devices provide differential (for the LVDS technology I/O
standard) and series on-chip termination to reduce reflections and
maintain signal integrity. On-chip termination simplifies board design by
minimizing the number of external termination resistors required.
Termination can be placed inside the package, eliminating small stubs
that can still lead to reflections.
Stratix II GX devices provide four types of termination:
■
■
■
■
Table 2–34
bank.
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL
2.5-V LVCMOS
1.8-V LVTTL
1.8-V LVCMOS
1.5-V LVTTL
1.5-V LVCMOS
SSTL-2 class I and II
SSTL-18 class I
SSTL-18 class II
1.8-V HSTL class I
1.8-V HSTL class II
1.5-V HSTL class I
1.2-V HSTL
Differential termination (R
Series termination (R
Series termination (R
Parallel termination (R
I/O Standard Support
shows the Stratix II GX on-chip termination support per I/O
S
S
) without calibration
) with calibration
T
) with calibration
Top and Bottom Banks
D
)
(3, 4, 7, 8)
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Altera Corporation
Left Bank (1, 2)
October 2007
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