EP2SGX90EF1152I4N Altera, EP2SGX90EF1152I4N Datasheet - Page 182

• Manufacturer Part Number: EP2SGX90EF1152I4N
• Description: Stratix II GX
• Manufacturer: Altera

Specifications of EP2SGX90EF1152I4N

• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / Rohs Status: Compliant

Operating Conditions
Figure 4–4. Transmitter Output Waveform
Figure 4–5. Maximum Receiver Input Pin Voltage
Note to
(1)
4–12
Stratix II GX Device Handbook, Volume 1
Note to
(1)
V
Table 4–7. Typical V
V
OD
C C H
The absolute V
Typical (mV)
Applicable to data rates from 600 Mbps to 6.375 Gbps. Specification is for measurement at the package ball.
TX = 1.5 V
Figure
Table
Single-Ended Waveform
Differential Waveform
Single-Ended Waveform
4–7:
4–5:
MAX
V MAX = V CM + V
OD
that the receiver input pins can tolerate is 2 V.
200
220
Setting, TX Term = 100 Ω
V
Tables 4–7
600 Mbps to 6.375 Gbps. The specification is for measurement at the
package ball.
CM
V
CM = 0.85 V
V
V
(single-ended p-p)max
(single-ended p-p)max
OD
400
430
2
through
V
OD
= 3.3 V/2
= 0.85 + 0.825 = 1.675 V (1)
600
625
Note (1)
4–12
V OD (diff peak-peak) = 2 x V OD (single-ended)
V
show the typical V
OD
Setting (mV)
800
830
V
OD
1000
1020
p − n = 0 V
Positive Channel (p)
Negative Channel (n)
Ground
Positive Channel (p)
Negative Channel (n)
Ground
OD
for data rates from
1200
1200
Altera Corporation
June 2009
1400
1350