EP2SGX90EF1152I4N Altera, EP2SGX90EF1152I4N Datasheet - Page 17
EP2SGX90EF1152I4N
Manufacturer Part Number
EP2SGX90EF1152I4N
Description
Stratix II GX
Manufacturer
Altera
Datasheet
1.EP2SGX90EF1152I4N.pdf
(316 pages)
Specifications of EP2SGX90EF1152I4N
Family Name
Stratix II GX
Number Of Logic Blocks/elements
90960
# I/os (max)
558
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520448
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2SGX90EF1152I4N
Manufacturer:
ALTERA
Quantity:
535
Part Number:
EP2SGX90EF1152I4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Figure 2–6. 16-Bit to 20-Bit Encoding Process
Altera Corporation
October 2007
CTRL[1..0]
MSB
19
j'
h'
18
g'
17
15
H'
16
f'
14
G'
15
i'
13
F'
Figure 2–5. 8B/10B Encoding Process
In single-width mode, the 8B/10B encoder generates a 10-bit code group
from the 8-bit data and 1-bit control identifier. In double-width mode,
there are two 8B/10B encoders that are cascaded together and generate a
20-bit (2 × 10-bit) code group from the 16-bit (2 × 8-bit) data + 2-bit
(2 × 1-bit) control identifier.
process. The 8B/10B encoder conforms to the IEEE 802.3 1998 edition
standards.
Upon power on or reset, the 8B/10B encoder has a negative disparity
which chooses the 10-bit code from the RD-column. However, the
running disparity can be changed via the tx_forcedisp and
tx_dispval ports.
14
e'
12
E'
d'
13
11
D'
Cascaded 8B/10B Conversion
MSB sent last
12
c'
10
C'
11
b'
9
j
B'
9
a'
10
h
8
H
7
A'
8
g
7
9
G
j
6
H
7
Figure 2–6
8B/10B Conversion
h
6
8
5
F
f
G
6
E
g
5
4
7
Stratix II GX Device Handbook, Volume 1
i
F
5
3
D
6
e
4
f
shows the 20-bit encoding
E
4
2
C
5
i
d
3
D
3
B
1
e
4
c
2
C
2
Stratix II GX Architecture
0
A
d
3
LSB sent first
b
1
B
1
+
c
2
a
0
A
0
ctrl
Parallel Data
b
1
LSB
a
0
2–9
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