PSB21384HV1.3 Infineon Technologies, PSB21384HV1.3 Datasheet - Page 40

• Manufacturer Part Number: PSB21384HV1.3
• Description: Telecom ICs AMuLaw/Speech CODEC w/ ST Transceiver
• Manufacturer: Infineon Technologies

Specifications of PSB21384HV1.3

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Data Sheet
2.1.2
The 8-bit parallel microcontroller interface with address decoding on chip allows an easy
and fast microcontroller access.
The parallel interface provides three types of P buses which are selected via pin ALE.
The bus operation modes with corresponding pins are listed in table 5.
Table 5
Bus Operation Modes
The occurrence of an edge on ALE, either positive or negative, at any time during the
operation immediately selects the interface type (3). A return to one of the other interface
types is possible only if a hardware reset is issued.
Note: If the multiplexed address/data bus type (3) is selected, the unused address pins
A read/write access to the registers can be done in multiplexed or non-multiplexed
mode.
In non-multiplexed mode the register address must be applied to the address bus (A0-
A7) for the data access via the data bus (D0-D7).
In multiplexed mode the address on the address bus (AD0-AD7) is latched in by ALE
before a read/write access via the address/data bus is performed.
Depending on the AMOD bit in the MODE2 register (see chapter 7.2.13) the direct or
indirect address mode can be selected.
The address mode after reset is the indirect address mode (AMOD = ’0’).
Reprogramming into the direct address mode (AMOD = ’1’) has to take place in the
indirect address mode. Figure 17 illustrates both register addressing modes.
Direct address mode (AMOD = ’1’): The register address to be read or written is directly
set in the way described above.
Indirect address mode (AMOD = ’0’): Only the LSB of the address line (A0) is used to
select either the address register (A0 = ’0’) or the data register (A0 = ’1’). The
microcontroller writes the register address to the ADDRESS register before it reads/
writes data from/to the corresponding DATA register.
In indirect address mode only the address line A0 is evaluated. The remaining address
lines have to be tied to logical ’1’.
Note: The CRAM back-up procedure (see chapter 4.8.2.1) only applies to the direct
(1) Motorola
(2) Siemens/Intel non-multiplexed
(3) Siemens/Intel multiplexed
A0-A7 must be tied to V
address mode
Bus Mode
Parallel Microcontroller Interface
DD
.
V
V
Edge
30
Pin ALE
DD
SS
Control Pins
CS, R/W, DS
CS, WR, RD
CS, WR, RD, ALE
PSB 21381/2
PSB 21383/4
Interfaces
2001-03-12