PSB21384HV1.3 Infineon Technologies, PSB21384HV1.3 Datasheet - Page 53

• Manufacturer Part Number: PSB21384HV1.3
• Description: Telecom ICs AMuLaw/Speech CODEC w/ ST Transceiver
• Manufacturer: Infineon Technologies

Specifications of PSB21384HV1.3

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.2.2.1.4 Synchronous Transfer
While looping, shifting and switching (see figure 28 and 29) the data can be accessed by
the controller between the synchronous transfer interrupt (STI) and the synchronous
transfer overflow interrupt (STOV).
The microcontroller access to the CDAxy registers can be synchronized by means of
four programmable synchronous transfer interrupts (STIxy) and synchronous transfer
overflow interrupts (STOVxy) in the STI register.
Depending on the DPS bit in the corresponding CDA_TSDPxy register the STIxy is
generated two (for DPS=’0’) or one (for DPS=’1’) BCL clock after the selected time slot
(CDA_TSDPxy.TSS). One BCL clock is equivalent to two DCL clocks.
A non masked synchronous transfer overflow (STOVx
appropriate STIx
bit ACKx
clocks (for DPS=’1’) before the time slot which is selected for the appropriate STOVx
If STIx
example a), c) and d) of figure 26).
If STIx
STIxy (see example b) and d) of figure 26).
Setting the corresponding bits in the MSTI (Mask Synchronous Transfer Interrupts)
register masks the STIxy and the STOVxy interrupt. The interrupt structure of the
synchronous transfer is shown in figure 25. Examples of the described synchronous
transfer interrupt controlling are illustrated in Figure 26. A read to the STI register clears
the STIxy and STOVxy interrupts.
.
Figure 25
Interrupt Structure of the Synchronous Data Transfer
Data Sheet
HDLC
TRAN
WOV
MOS
MASK
TIN
CIC
ST
INT
1
1
y
y
1
1
1
y
is masked but STOVx
1
and STOVx
in the ASTI register is set to ’1’ one BCL clock (for DPS=’0’) or zero BCL
1
y
HDLC
TRAN
MOS
WOV
ISTA
1
CIC
TIN
ST
is not acknowledged in time. The STIx
1
y
1
are not masked STOVx
1
y
1
is not masked, STOVx
STOV20
STOV21
STOV11
STOV10
MSTI
STI20
STI11
STI10
STI21
43
1
y
1
0
is only related to STIx
STOV10
STOV20
STOV11
STOV21
y
STI21
STI20
STI11
STI10
0
0
) interrupt is generated if the
STI
1
y
y
0
1
is related to each enabled
is acknowledged in time if
ACK10
PSB 21381/2
PSB 21383/4
ACK21
ACK11
ACK20
ASTI
Interfaces
2001-03-12
1
y
1
(see
0
y
0
.