HUFA75429D3ST Fairchild Semiconductor, HUFA75429D3ST Datasheet - Page 8

• Manufacturer Part Number: HUFA75429D3ST
• Description: MOSFET N-CH 60V 20A DPAK
• Manufacturer: Fairchild Semiconductor
• Series: UltraFET™r

Specifications of HUFA75429D3ST

• Fet Type: MOSFET N-Channel, Metal Oxide
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 25 mOhm @ 20A, 10V
• Drain To Source Voltage (vdss): 60V
• Current - Continuous Drain (id) @ 25° C: 20A
• Vgs(th) (max) @ Id: 4V @ 250µA
• Gate Charge (qg) @ Vgs: 85nC @ 20V
• Input Capacitance (ciss) @ Vds: 1090pF @ 25V
• Power - Max: 125W
• Mounting Type: Surface Mount
• Package / Case: DPak, TO-252 (2 leads+tab), SC-63
• Configuration: Single
• Transistor Polarity: N-Channel
• Resistance Drain-source Rds (on): 0.021 Ohms
• Drain-source Breakdown Voltage: 60 V
• Gate-source Breakdown Voltage: +/- 20 V
• Continuous Drain Current: 20 A
• Power Dissipation: 125 W
• Maximum Operating Temperature: + 175 C
• Mounting Style: SMD/SMT
• Fall Time: 33 ns
• Minimum Operating Temperature: - 55 C
• Rise Time: 39 ns
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

©2003 Fairchild Semiconductor Corporation
PSPICE Electrical Model
.SUBCKT HUFA75429D3S 2 1 3 rev February 2002
CA 12 8 1.9e-9
CB 15 14 1.9e-9
CIN 6 8 9.7e-10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 65
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LGATE 1 9 3.54e-9
LDRAIN 2 5 1e-9
LSOURCE 3 7 2.21e-9
RLGATE 1 9 35.4
RLDRAIN 2 5 10
RLSOURCE 3 7 22.1
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 6.5e-3
RGATE 9 20 2
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 1.1e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*100),5))}
.MODEL DBODYMOD D (IS = 1.6e-12 N=1.02 RS = 8.1e-3 TRS1 = 3e-3 TRS2 = 2e-6 CJO = 1.43e-9 TT = 3e-8 M = 0.53 XTI=5.5)
.MODEL DBREAKMOD D (RS = 2e-1 TRS1 = 1e-3 TRS2 = -8.9e-6)
.MODEL DPLCAPMOD D (CJO = 1.4e-9 IS = 1e-30 N = 10 M = 0.79)
.MODEL MmedMOD NMOS (VTO=3 KP=4.5 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2)
.MODEL MstroMOD NMOS (VTO=3.6 KP=40 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=2.66 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2e1 RS=0.1)
.MODEL RBREAKMOD RES (TC1 =1.2e-3 TC2 = 1e-7)
.MODEL RDRAINMOD RES (TC1 = 1.2e-2 TC2 = 2.3e-5)
.MODEL RSLCMOD RES (TC1 = 8e-3 TC2 = 1e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 8e-6)
.MODEL RVTEMPMOD RES (TC1 = -3e-3 TC2 = -2e-6)
.MODEL RVTHRESMOD RES (TC1 = -2e-3 TC2 = -1e-5)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -8 VOFF= -3.5)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.5 VOFF= -8)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.1 VOFF= 0.5)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= -1.1)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
GATE
1
RLGATE
LGATE
9
RGATE
CA
12
20
+
EVTEMP
S1A
S1B
ESG
18
22
EGS
13
8
+
-
-
13
6
8
10
+
+
-
-
14
13
6
8
RSLC2
6
S2A
S2B
DPLCAP
EVTHRES
+
EDS
19
8
15
CB
CIN
-
+
-
5
8
51
5
5
+
-
MSTRO
14
51
21
RDRAIN
RSLC1
50
ESLC
16
8
MMED
8
EBREAK
IT
DBREAK
RSOURCE
17
MWEAK
RVTHRES
RBREAK
11
+
-
17
18
7
+
18
-
22
RVTEMP
19
RLSOURCE
DBODY
LSOURCE
VBAT
RLDRAIN
LDRAIN
SOURCE
DRAIN
2
3
Rev. A1