LE58QL021BVC Zarlink, LE58QL021BVC Datasheet - Page 10

• Manufacturer Part Number: LE58QL021BVC
• Description: QUAD, SLAC, PROG CODEC, 3.3V, 20 I/0, PQT44, LEAD FREE
• Manufacturer: Zarlink

PIN DESCRIPTIONS
AGND, DGND
CD1
CD2
C3
C4
C5
CHCLK
CS
DCLK
DIO
Pin Names
1
1
1
–C3
–C4
–C5
1
1
–CD1
–CD2
4
4,
4
,
4
4
,
Power
Inputs/Outputs
Inputs/Outputs
Output
Input
Input
Input/Output
Type
Separate analog and digital grounds are provided to allow noise isolation; however, the two
grounds are connected inside the part, and the grounds must also be connected together on
the circuit board.
Control and Data. CD1 and CD2 are TTL compatible programmable Input or Output (I/O)
ports. They can be used to monitor or control the state of the SLIC drivce or any other device
associated with the subscriber line interface. The direction, input or output, is programmed
using MPI Command 54/55h. As outputs, CD1 and CD2 can be used to control relays,
illuminate LEDs, or perform any other function requiring a latched TTL compatible signal for
control. The output state of CD1 and CD2 is written using MPI Command 52h. As inputs, CD1
and CD2 can be processed by the QLSLAC device (if programmed to do so). CD1 can be
debounced before it is made available to the system. The debounce time is programmable
from 0 to 15 ms in 1 ms increments using MPI Command C8/C9h. CD2 can be filtered using
the up/down counter facility and programming the sampling interval using MPI Command E8/
E9h.
Additionally, CD1 can be demultiplexed into two separate inputs using the E1 demultiplexing
function. The E1 demultiplexing function of the QLSLAC device was designed to interface
directly to Legerity SLIC devices supporting the ground key function. With the proper Legerity
SLIC device and the E1 function of the QLSLAC device enabled, the CD1 bit can be
demultiplexed into an Off-Hook/Ring Trip signal and Ground Key signal. In the demultiplex
mode, the second bit, Ground Key, takes the place of the CD2 as an input. The demultiplexed
bits can be debounced (CD1) or filtered (CD2) as explained previously. A more complete
description of CD1, CD2, debouncing, and filtering functions is contained in
QLSLAC Device, on page
Once the CD1 and CD2 inputs are processed (Debounced, Filtered and/or Demultiplexed) by
the QLSLAC device, the information can be accessed by the system in two ways: 1) on a per
channel basis along with C3, C4, and C5 of the specific channel using MPI Command 53h, or
2) by using MPI Command 4D/4Fh, which obtain the CD1 and CD2 bits from all four channels
simultaneously. This feature reduces the processor overhead and the time required to retrieve
time-critical signals from the line circuits, such as off-hook and ring trip. With this feature,
hookswitch status and ring trip information, for example, can be obtained from all four
channels of a QLSLAC device with one read command.
Control. C3, C4, and C5 are TTL-compatible programmable Input or Output (I/O) ports. They
can be used to monitor or control the state of the SLIC device or any other device associated
with subscriber line interface. The direction, input or output, is programmed using MPI
Command 54/55h. As outputs, C3, C4, and C5 can be used to control relays, illuminate LEDs,
or perform any other function requiring a latched TTL compatible signal for control. The output
state of C3, C4, and C5 is written using MPI Command 52h. As inputs, C3, C4, and C5 can
be accessed by the system by using MPI Command 53h.
The Le58QL021 QLSLAC device contains a single PCM highway and five programmable I/
Os per channel (CD1, CD2, C3, C4, and C5) in a 44-pin PLCC or TQFP package. In the
Le58QL02 QLSLAC device, the C5
PCM highways and a chopper clock output in a 44-pin PLCC or TQFP package. In the
Le58QL031 QLSLAC device, the C3
eliminated, enabling a single PCM highway and two control and data I/Os (CD1, CD2) per
channel in a 32-pin PLCC package.
Chopper Clock. This output provides a 256 kHz or a 292.57 kHz, 50% duty cycle, TTL-
compatible clock for use by up to four SLIC devices with built-in switching regulators. The
CHCLK frequency is synchronous to the master clock, but the phase relationship to the master
clock is random. The chopper clock is not available in all package types.
Chip Select. The Chip Select input (active Low) enables the device so that control data can
be written to or read from the part. The channels selected for the write or read operation are
enabled by writing 1 s to the appropriate bits in the Channel Enable Register of the QLSLAC
device prior to the command. See EC1, EC2, EC3, and EC4 of the Command
Read Channel Enable and Operating Mode Register, on page 44
Select is held Low for 16 rising edges of DCLK, a hardware reset is executed when Chip
Select returns High.
Data Clock. The Data Clock input shifts data into and out of the microprocessor interface of
the QLSLAC device. The maximum clock rate is 8.192 MHz.
Data. Control data is serially written into and read out of the QLSLAC device via the DIO pin,
with the most significant bit first. The Data Clock determines the data rate. DIO is high
impedance except when data is being transmitted from the QLSLAC device.
Zarlink Semiconductor Inc.
10
27.
1
, C5
1
–C5
Description
2
, C5
1
, C3
3
, and C5
2
–C5
2
, C3
4
I/Os are eliminated, enabling dual
3
–C5
3
, and C3
for more information. If Chip
4
–C5
Operating the
4
4A/4Bh Write/
I/Os are