LE58QL021BVC Zarlink, LE58QL021BVC Datasheet - Page 36

• Manufacturer Part Number: LE58QL021BVC
• Description: QUAD, SLAC, PROG CODEC, 3.3V, 20 I/0, PQT44, LEAD FREE
• Manufacturer: Zarlink

Signaling on the PCM Highway
If the SMODE bit is set in the Configuration register (Command 46/47h), each data point occupies two consecutive time slots.
The first time slot contains A-law or µ-law data and the second time slot contains the following information:
Bit 7 of the signaling byte appears immediately after bit 0 of the data byte. A-law or µ-law Companded state must be specified in
order to put signaling information on the PCM highway. The signaling time slot remains active, even when the channel is inactive.
Robbed-Bit Signaling Compatibility
The QLSLAC device supports robbed bit signaling compatibility. Robbed bit signaling allows periodic use of the least significant
bit (LSB) of the receive path PCM data to be used to carry signaling information. In this scheme, separate circuitry within the line
card or system intercepts this bit out of the PCM data stream and uses this bit to control signaling functions within the system.
The QLSLAC device does not perform any processing of any of the robbed bits during this operation; it simply allows for the
robbed bit presence by performing the LSB substitution.
If the RBE bit is set in the Channel Enable and Operating Mode register (Command 4A/4Bh), then the robbed-bit signaling
compatibility mode is enabled. Robbed-bit signaling is only available in the µ-law companding mode of the device. Also, only the
receive (digital-to-analog) path is involved. There is no change of operation to the transmit path and PCM data coming out of the
QLSLAC device will always contain complete PCM byte data for each time slot, regardless of robbed-bit signaling selection.
In the absence of actual PCM data for the affected time slots, there is an uncertainty of the legitimate value of this bit to accurately
reconstruct the analog signal. This bit can always be assumed to be a 1 or 0; hence, the reconstructed signal is correct half the
time. However, the other half of the time, there is an unacceptable reconstruction error of a significance equal to the value
weighting of the LSB. To reduce this error and provide compatibility with the robbed bit signaling scheme, when in the robbed-bit
signaling mode, the QLSLAC device ignores the LSB of each received PCM byte and replaces its value in the expander with a
value of half the LSB’s weight. This then guarantees the reconstruction is in error by only half this LSB weight. In the expander,
the eight bits of the companded PCM byte are expanded into linear PCM data of several more bits within the internal signal
processing path of the device. Therefore, accuracy is not limited to the weight of the LSB, and a weight of half this value is
realizable.
When this robbed-bit mode is selected, not every frame contains bits for signaling, and therefore not every byte requires its LSB
substituted with the half-LSB weight. This substitution only occurs for valid PCM time slots within frames for which this robbed bit
has been designated. To determine which time slots are affected, the device monitors the frame sync (FS) pulse. The current
frame is a robbed-bit frame and this half-LSB value is used only when this criteria is met:
The frame sync pulse is sampled on the falling edge of PCLK. As shown in Figure 25, if the above criteria is met, and if FS is
high for two consecutive falling edges of PCLK then low for the third falling edge, it is considered a robbed-bit frame. Otherwise,
it is a normal frame.
Bit 7:
Bit 6:
Bits 5–3:
Bit 2:
Bits 1–0:
The RBE bit is set, and
The device is in the µ-law companding mode, and
The current frame sync pulse (FS) is two PCLK cycles long, and
The previous frame sync pulse (FS) was not two PCLK cycles long.
Debounced CD1 bit (usually hook switch)
CD2 bit or CD1B bit
Reserved
CFAIL
Reserved
Zarlink Semiconductor Inc.
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