LE58QL021BVC Zarlink, LE58QL021BVC Datasheet - Page 39

• Manufacturer Part Number: LE58QL021BVC
• Description: QUAD, SLAC, PROG CODEC, 3.3V, 20 I/0, PQT44, LEAD FREE
• Manufacturer: Zarlink

Commands are provided to assign values to the following global chip parameters:
Commands are provided to read values from the following global chip status monitors:
Microprocessor Interface Description
The following description of the MPI (Microprocessor Interface) is valid for channels 1 – 4. If desired, multiple channels can be
programmed simultaneously with identical information by setting multiple Channel Enable bits. Channel enables are contained
in the Channel Enable register and written or read using MPI Command 4A/4Bh. If multiple Channel Enable bits are set for a read
operation, only data from the first enabled channel will be read.
The MPI physically consists of a serial data input/output (DIO), a data clock (DCLK), and a chip select (CS). Individual Channel
Enable bits EC1, EC2, EC3, and EC4 are stored internally in the Channel Enable register of the QLSLAC device. The serial
input consists of 8-bit commands that can be followed with additional bytes of input data, or can be followed by the QLSLAC
device sending out bytes of data. All data input and output is MSB (D7) first and LSB (D0) last. All data bytes are read or written
one at a time, with CS going High for at least a minimum off period before the next byte is read or written. Only a single channel
should be enabled during read commands.
All commands that require additional input data to the device must have the input data as the next N words written into the device
(for example, framed by the next N transitions of CS). All unused bits must be programmed as 0 to ensure compatibility with future
parts. All commands that are followed by output data will cause the device to output data for the next N transitions of CS going
Low. The QLSLAC device will not accept any commands until all the data has been shifted out. The output values of unused bits
are not specified.
An MPI cycle is defined by transitions of CS and DCLK. If the CS lines are held in the High state between accesses, the DCLK
may run continuously with no change to the internal control data. Using this method, the same DCLK can be run to a number of
Table 4. Channel Monitors
Table 5. Global Chip Parameters
Table 6. Global Chip Status Monitors
Parameter
CD1–C5
CMODE
Monitor
SMODE
VMODE
Monitor
MCDx
CFAIL
CD1B
XDAT
CSEL
CD
INTM
RCS
CHP
ECH
DSH
RCN
TCS
RBE
EE1
E1P
EC
XE
x
C
C
Read SLIC device inputs
Multiplexed SLIC device Input
Transmit PCM data
Transmit PCM Clock Edge
Receive clock slot
Transmit clock slot
Interrupt Output Drive Mode
Chopper Clock Frequency
Enable Chopper Clock Output
Select Signaling on the PCM Highway
Select Master Clock Mode
Select Master Clock Frequency
Robbed Bit Enable
VOUT Mode
Channel Enable Register
Debounce Time for CD1
Enable E1 Output
E1 Polarity
Interrupt Mask Register
Real Time Data Register
Clock Failure Bit
Revision Code Number
Zarlink Semiconductor Inc.
Description
Description
Description
39
C8/C9h
C8/C9h
C8/C9h
C8/C9h
6C/6Dh
4A/4Bh
4A/4Bh
4A/4Bh
4D/4Fh
44/45h
44/45h
44/45h
46/47h
46/47h
46/47h
46/47h
46/47h
54/55h
CDh
MPI
53h
53h
MPI
MPI
73h