LE58QL021BVC Zarlink, LE58QL021BVC Datasheet - Page 46

• Manufacturer Part Number: LE58QL021BVC
• Description: QUAD, SLAC, PROG CODEC, 3.3V, 20 I/0, PQT44, LEAD FREE
• Manufacturer: Zarlink

Channel Status (Read status only, write as 0)
Clock Fail (Read status only, write as 0)
I/O Direction (Read/Write)
Pins CD1, CD2, and C3 through C5 are set to Input or Output modes individually. Pins C3–C5 are not available on the
Le58QL031 QLSLAC device, and C5 is available only on the Le58QL021 QLSLAC device.
* Power Up and Hardware Reset (RST) Value = 00h
60/61h Write/Read Operating Functions
Linear Code
A-law or µ-law
GR Filter
GX Filter
X Filter
R Filter
Z Filter
B Filter
* Power Up and Hardware Reset (RST) Value = 00h.
Command
I/O Data
R/W = 0: Write
R/W = 1: Read
CSTAT = 0
CSTAT = 1
CFAIL* = 0
CFAIL = 1
* The CFAIL bit is independent of the Channel Enable Register.
IOD5 = 0*
IOD5 = 1
IOD4 = 0*
IOD4 = 1
IOD3 = 0*
IOD3 = 1
IOD2 = 0*
IOD2 = 1
IOD1 = 0*
IOD1 = 1
C/L = 0*
C/L = 1
A/µ = 0*
A/µ = 1
EGR = 0*
EGR = 1
EGX = 0*
EGX = 1
EX = 0*
EX = 1
ER = 0*
ER = 1
EZ = 0*
EZ = 1
EB = 0*
EB = 1
Channel is inactive (Standby state).
Channel is active.
The internal clock is synchronized to frame synch.
The internal clock is not synchronized to frame synch.
C5 is an input
C5 is an output
C4 is an input
C4 is an output
C3 is an input
C3 is an output
CD2 is an input
CD2 is an output
CD1 is an input
CD1 is an output
Compressed coding
Linear coding
A-law coding
µ-law coding
Default GR filter enabled
Programmed GR filter enabled
Default GX filter enabled
Programmed GX filter enabled
Default X filter enabled
Programmed X filter enabled
Default R filter enabled
Programmed R filter enabled
Default Z filter enabled
Programmed Z filter enabled
Default B filter enabled
Programmed B filter enabled
C/L
D
0
7
Zarlink Semiconductor Inc.
A/µ
D
1
6
46
EGR
D
1
5
EGX
D
0
4
EX
D
0
3
ER
D
0
2
EZ
D
0
1
R/W
EB
D
0