LE58QL021BVC Zarlink, LE58QL021BVC Datasheet - Page 27

• Manufacturer Part Number: LE58QL021BVC
• Description: QUAD, SLAC, PROG CODEC, 3.3V, 20 I/0, PQT44, LEAD FREE
• Manufacturer: Zarlink

OPERATING THE QLSLAC DEVICE
The following sections describe the operation of the four independent channels of the QLSLAC device. The description is valid
for channel 1, 2, 3, or 4; consequently, the channel subscripts have been dropped. For example, VOUT refers to either VOUT1,
VOUT2, VOUT3, or VOUT4.
Power-Up Sequence
The recommended QLSLAC device power-up sequence is to apply:
1.
2.
3.
The software initialization should then include:
1.
2.
3.
4.
If the power supply (VCCD) falls below an internal threshold, the device is reset and will require complete reprogramming with
the above sequence. A reset may be initiated by connection of a logic Low to the RST pin, or if chip select (CS) is held low for
16 rising edges of DCLK, a hardware reset is generated when CS returns high. The RST pin may be tied to VCCD if it is not used
in the system.
Channel Enable (EC) Register
A channel enable register has been implemented in the QLSLAC device in order to reduce the effort required to address
individual or multiple channels of the QLSLAC device. The register is written using MPI Command 4A/4Bh. Each bit of the register
is assigned to one unique channel, bit 0 for channel 1, bit 1 for channel 2, bit 2 for channel 3, and bit 3 for channel 4. The channel
or channels are enabled when their corresponding enable bits are High. All enabled channels will receive the data written to the
QLSLAC device. This enables a Broadcast mode (all channels enabled) to be implemented simply and efficiently, and multiple
channel addressing is accomplished without increasing the number of I/O pins on the device. The Broadcast mode can be further
enhanced by providing the ability to select many chips at once; however, care must be taken not to enable more than one chip
in the Read state. This can lead to an internal bus contention, in which excess power is dissipated. (Bus contention will not
damage the device.)
SLIC Device Control and Data Lines
The QLSLAC device has up to five SLIC device programmable digital input/output pins per channel (CD1–C5). Each of these
pins can be programmed as either an input or an output using the I/O Direction register, Command 54/55h (see Figure 21). The
output latches can be written with Command 52h; however, only those bits programmed as outputs will actually drive the pins.
The inputs can be read with Command 53h. If a pin is programmed as an output, the data read from it will be the contents of the
output latch. It is recommended that any of the SLIC device input/output control and data pins, which are to be programmed as
outputs, be written to their desired state via Command 52h before writing the data which configures them as outputs with the I/
O direction register Command 54/55h. This ensures that when the output is activated, it is already in the correct state, and will
prevent unwanted data from being driven from the SLIC device output pins. It is possible to make a SLIC device control output
pull up to a non-standard voltage (V < 5.25 V) by connecting a resistor from the output to the desired voltage, sending zero to the
output, and using the DIO bit to tri-state the output.
Clock Mode Operation
The QLSLAC device operates with multiple clock signals. The master clock is used for internal timing including operation of the
digital signal processing and may be derived from either the MCLK or PCLK source. When MCLK is used as the master clock, it
should be synchronous to FS. The allowed frequencies are listed under Command 46/47h.
The PCM clock (PCLK) is used for PCM timing and is an integer multiple of the frame sync frequency. The internal master clock
can be optionally derived from the PCLK source by setting the CMODE bit (bit 4, Command 46/47h) to one. In this mode, the
MCLK/E1 pin is free to be used as an E1 signal output. Clock mode options and E1 output functions are shown in Figure 20.
Analog and digital ground
VCC, signal connections, and Low on RST
High on RST
Wait 1 ms.
Select master clock frequency and source (Command 46/47h). This should turn off the CFAIL bit (Command 55h) within
400 µs.
Program filter coefficients and other parameters as required.
Activate (Command 0Eh).
Zarlink Semiconductor Inc.
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