LE58QL021BVC Zarlink, LE58QL021BVC Datasheet - Page 44

• Manufacturer Part Number: LE58QL021BVC
• Description: QUAD, SLAC, PROG CODEC, 3.3V, 20 I/0, PQT44, LEAD FREE
• Manufacturer: Zarlink

4A/4Bh Write/Read Channel Enable and Operating Mode Register
Robbed-bit Mode
VOUT Mode
Low Power Mode
Channel Enable 4
Channel Enable 3
Channel Enable 2
Channel Enable 1
* Power Up and Hardware Reset (RST) Value = 0Fh.
4D/4Fh Read Real-Time Data Register
Real Time Data
This command does not depend on the state of the Channel Enable Register.
Command
I/O Data
Command
Output Data
R/W = 0: Write
R/W = 1: Read
C = 0: Do not clear interrupt
C = 1: Clear interrupt
This register reads real-time data with or without clearing the interrupt.
RSVD
RBE = 0*
RBE = 1
VMODE = 0*
VMODE = 1
LPM
EC4 = 0
EC4 = 1*
EC3 = 0
EC3 = 1*
EC2 = 0
EC2 = 1*
EC1 = 0
EC1 = 1*
CDA1
CDB1
CDA2
CDB2
CDA3
CDB3
CDA4
CDB4
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
Robbed-bit Signaling mode is disabled.
Robbed-bit Signaling mode is enabled on PCM receiver if
VOUT = VREF through a resistor when channel is deactivated
VOUT high impedance when channel is deactivated.
LPM reduced the power in the QSLAC device, but it is not needed and not used in the
QLSLAC device
Disabled, channel 4 cannot receive commands
Enabled, channel 4 can receive commands
Disabled, channel 3 cannot receive commands
Enabled, channel 3 can receive commands
Disabled, channel 2 cannot receive commands
Enabled, channel 2 can receive commands
Disabled, channel 1 cannot receive commands
Enabled, channel 1 can receive commands
Debounced data bit 1 on channel 1
Data bit 2 or multiplexed data bit 1 on channel 1
Debounced data bit 1 on channel 2
Data bit 2 or multiplexed data bit 1 on channel 2
Debounced data bit 1 on channel 3
Data bit 2 or multiplexed data bit 1 on channel 3
Debounced data bit 1 on channel 4
Data bit 2 or multiplexed data bit 1 on channel 4
RSVD
CDB4
D
D
0
0
7
7
Zarlink Semiconductor Inc.
RBE
CDA4
D
1
D
6
1
6
VMODE
44
CDB3
D
D
0
0
5
5
CDA3
LPM
D
D
0
0
4
4
CDB2
EC4
D
D
1
1
3
3
CDA2
EC3
D
D
1
0
2
2
µ
-law is selected.
CDB1
EC2
D
D
C
1
1
1
CDA1
R/W
EC1
D
D
1
0
0