LE58QL021BVC Zarlink, LE58QL021BVC Datasheet - Page 43

• Manufacturer Part Number: LE58QL021BVC
• Description: QUAD, SLAC, PROG CODEC, 3.3V, 20 I/0, PQT44, LEAD FREE
• Manufacturer: Zarlink

46/47h Write/Read Chip Configuration Register
Interrupt Mode
Chopper Clock Control
PCM Signaling Mode
Clock Source Mode
The master clock frequency can be selected by CSEL. The master clock frequency selection affects all channels.
Master Clock Frequency
These commands do not depend on the state of the Channel Enable Register.
* Power Up and Hardware Reset (RST) Value = 9Ah.
Command
I/O Data
R/W = 0: Write
R/W = 1: Read
INTM = 0
INTM = 1*
CHP = 0*
CHP = 1
SMODE = 0*
SMODE = 1
CMODE = 0
CMODE = 1*
CSEL = 0000
CSEL = 0001
CSEL = 0010
CSEL = 0011
CSEL = 01xx
2 x 1.544 MHz, or 2 x 2.048 MHz)
CSEL = 10xx
4 x 1.544 MHz, or 4 x 2.048 MHz)
CSEL = 11xx
CSEL = 1010*
TTL-compatible output
Open drain output
Chopper Clock is 256 kHz (2048/8 kHz)
Chopper Clock is 292.57 kHz (2048/7 kHz)
No signaling on PCM highway
Signaling on PCM highway
MCLK used as master clock; no E1 multiplexing allowed
PCLK used as master clock; E1 multiplexing allowed if enabled in commands C8/C9h.
1.536 MHz
1.544 MHz
2.048 MHz
Reserved
Two times frequency specified above (2 x 1.536 MHz,
Four times frequency specified above (4 x 1.536 MHz,
Reserved
8.192 MHz is the default
INTM
D
0
7
CHP
D
Zarlink Semiconductor Inc.
1
6
SMODE
D
0
5
43
CMODE
D
0
4
CSEL3
D
0
3
CSEL2
D
1
2
CSEL1
D
1
1
CSEL0
R/W
D
0