LE58QL021BVC Zarlink, LE58QL021BVC Datasheet - Page 6

• Manufacturer Part Number: LE58QL021BVC
• Description: QUAD, SLAC, PROG CODEC, 3.3V, 20 I/0, PQT44, LEAD FREE
• Manufacturer: Zarlink

PRODUCT DESCRIPTION
The QLSLAC device performs the codec/filter and two-to-four-wire conversion functions required of the subscriber line interface
circuitry in telecommunications equipment. These functions involve converting audio signals into digital PCM samples and
converting digital PCM samples back into audio signals. During conversion, digital filters are used to band limit the voice signals.
All of the digital filtering is performed in digital signal processors operating from a master clock, which can be derived either from
PCLK or MCLK.
Four independent channels allow the QLSLAC device to function as four SLAC™ devices. For programming information, each
channel has its own enable bit (EC1, EC2, EC3, and EC4) to allow individual channel programming. If more than one Channel
Enable bit is High or if all Channel Enable bits are High, all channels enabled will receive the programming information written;
therefore, a Broadcast mode can be implemented by simply enabling all channels in the device to receive the information. The
Channel Enable bits are contained in the Channel Enable (EC) register, which is written and read using Command 4A/4Bh. The
Broadcast mode is useful in initializing QLSLAC devices in a large system.
The user-programmable filters set the receive and transmit gain, perform the transhybrid balancing function, permit adjustment
of the two-wire termination impedance, and provide equalization of the receive and transmit paths. All programmable digital filter
coefficients can be calculated using the WinSLAC™ software.
Data transmitted or received on the PCM highway can be 8-bit companded code (with an optional 8-bit signaling byte in the
transmit direction) or 16-bit linear code. The 8-bit codes appear 1 byte per time slot, while the 16-bit code appears in two
consecutive time slots. The compressed PCM codes can be either 8-bit companded A-law or µ-law. The PCM data is read from
and written to the PCM highway in user-programmable time slots at rates of 128 kHz to 8.192 MHz. The transmit clock edge and
clock slot can be selected for compatibility with other devices that can be connected to the PCM highway.
Three configurations of the QLSLAC device are offered with single or dual PCM highways. The Le58QL02 and Le58QL021
QLSLAC devices with dual and single PCM highways respectively are available in the 44-pin packages. The Le58QL031JC
QLSLAC device is a single PCM highway version in a 32-pin PLCC package.
BLOCK DESCRIPTIONS
Clock and Reference Circuits
This block generates a master clock and a frame sync signal for the digital circuits. It also generates an analog reference voltage
for the analog circuits.
Microprocessor Interface (MPI)
This block communicates with the external control microprocessor over a serial interface. It passes user control information to
the other blocks, and it passes status information from the blocks to the user. In addition, this block contains the reset circuitry.
Time Slot Assigner (TSA)
This block communicates with the PCM highway, where the PCM highway is a time division mutiplexed bus carrying the digitized
voice samples. The block implements programmable time slots and clocking arrangements in order to achieve a first layer of
switching. Internally, this block communicates with the Signal Processing Channels (CHx).
Signal Processing Channels (CHx)
These blocks do the transmission processing for the voice channels. Part of the processing is analog and is interfaced to the VIN
and VOUT pins. The remainder of the processing is digital and is interfaced to the Time Slot Assigner (TSA) block.
SLIC Device Interface (SLI)
This block communicates digitally with the SLIC device circuits. It sends control bits to the SLIC devices to control modes and to
operate LEDs and optocouplers. It also accepts supervision information from the SLIC devices and performs some filtering.
Table 1. QLSLAC Device Configurations
PCM Highway
Single
Single
Dual
Programmable I/O
per Channel
Four I/O
Five I/O
Two I/O
Zarlink Semiconductor Inc.
Chopper Clock
6
Yes
No
No
44 PLCC
44 PLCC/TQFP
32 PLCC
Package
Le58QL02JC
Le58QL021JC (or VC)
Le58QL031JC
Part Number