MT48LC16M16A2P-75 L:D TR Micron Technology Inc, MT48LC16M16A2P-75 L:D TR Datasheet - Page 15

• Manufacturer Part Number: MT48LC16M16A2P-75 L:D TR
• Description: DRAM Chip SDRAM 256M-Bit 16Mx16 3.3V 54-Pin TSOP-II T/R
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC16M16A2P-75 L:D TR

• Package: 54TSOP-II
• Density: 256 Mb
• Address Bus Width: 15 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Clock Rate: 133 MHz
• Maximum Random Access Time: 6|5.4 ns
• Operating Temperature: 0 to 70 °C
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 256M (16Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 54-TSOP II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1191-2

Table 4: Pin and Ball Descriptions
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
CAS#, RAS#, WE#
DQML, DQMH
LDQM, UDQM
DQ[15:0]
Symbol
(54-ball)
DQ[7:0]
DQ[3:0]
BA[1:0]
A[12:0]
x4, x8:
DQM
V
V
x16:
x16:
CLK
CKE
V
CS#
x8:
x4:
V
NC
DDQ
SSQ
DD
SS
Supply DQ power: DQ power to the die for improved noise immunity.
Supply DQ ground: DQ power to the die for improved noise immunity.
Supply Power supply: +3.3V ±0.3V.
Supply Ground.
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
I/O
–
Description
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive
edge of CLK. CLK also increments the internal burst counter and controls the output registers.
Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the
clock provides precharge power-down and SELF REFRESH operation (all banks idle), active pow-
er-down (row active in any bank), or CLOCK SUSPEND operation (burst/access in progress).
CKE is synchronous except after the device enters power-down and self refresh modes, where
CKE becomes asynchronous until after exiting the same mode. The input buffers, including
CLK, are disabled during power-down and self refresh modes, providing low standby power.
CKE may be tied HIGH.
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decod-
er. All commands are masked when CS# is registered HIGH, but READ/WRITE bursts already in
progress will continue, and DQM operation will retain its DQ mask capability while CS# is
HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is consid-
ered part of the command code.
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered.
Input/output mask: DQM is sampled HIGH and is an input mask signal for write accesses and
an output enable signal for read accesses. Input data is masked during a WRITE cycle. The
output buffers are High-Z (two-clock latency) during a READ cycle. LDQM corresponds to
DQ[7:0], and UDQM corresponds to DQ[15:8]. LDQM and UDQM are considered same-state
when referenced as DQM.
Bank address input(s): BA[1:0] define to which bank the ACTIVE, READ, WRITE, or PRECHARGE
command is being applied.
Address inputs: A[12:0] are sampled during the ACTIVE command (row address A[12:0]) and
READ or WRITE command (column address A[9:0] and A11 for x4; A[9:0] for x8; A[8:0] for x16;
with A10 defining auto precharge) to select one location out of the memory array in the re-
spective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to
be precharged (A10 HIGH) or bank selected by BA[1:0] (LOW). The address inputs also provide
the op-code during a LOAD MODE REGISTER command.
Data input/output: Data bus for x16 (pins 4, 7, 10, 13, 42, 45, 48, and 51 are NC for x8; and
pins 2, 4, 7, 8, 10, 13, 42, 45, 47, 48, 51, and 53 are NC for x4).
Data input/output: Data bus for x8 (pins 2, 8, 47, 53 are NC for x4).
Data input/output: Data bus for x4.
These should be left unconnected. For x4 and x8 parts, G1 is a no connect, but may be used as
A12 in future designs.
Pin and Ball Assignments and Descriptions
15
Micron Technology, Inc. reserves the right to change products or specifications without notice.
256Mb: x4, x8, x16 SDRAM
© 1999 Micron Technology, Inc. All rights reserved.