MT48LC16M16A2P-75 L:D TR Micron Technology Inc, MT48LC16M16A2P-75 L:D TR Datasheet - Page 70

• Manufacturer Part Number: MT48LC16M16A2P-75 L:D TR
• Description: DRAM Chip SDRAM 256M-Bit 16Mx16 3.3V 54-Pin TSOP-II T/R
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC16M16A2P-75 L:D TR

• Package: 54TSOP-II
• Density: 256 Mb
• Address Bus Width: 15 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Clock Rate: 133 MHz
• Maximum Random Access Time: 6|5.4 ns
• Operating Temperature: 0 to 70 °C
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 256M (16Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 54-TSOP II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1191-2

Figure 39: READ With Auto Precharge Interrupted by a READ
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Internal
states
Command
Note:
Address
Bank m
Bank n
CLK
DQ
registered. The last valid data WRITE to bank n will be data registered one clock prior to
a WRITE to bank m (see Figure 46 (page 76)).
1. DQM is LOW.
Page active
NOP
T0
READ - AP
Page active
Bank n,
Bank n
T1
Col a
READ with burst of 4
T2
CL = 3 (bank n)
NOP
70
READ - AP
Bank m,
T3
Bank m
Col d
Interrupt burst, precharge
READ with burst of 4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T4
CL = 3 (bank m)
NOP
t
RP - bank n
D
OUT
T5
NOP
256Mb: x4, x8, x16 SDRAM
D
OUT
PRECHARGE Operation
T6
NOP
D
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OUT
Idle
T7
Don’t Care
NOP
t RP - bank m
D
Precharge
OUT