MT48LC16M16A2P-75 L:D TR Micron Technology Inc, MT48LC16M16A2P-75 L:D TR Datasheet - Page 77

DRAM Chip SDRAM 256M-Bit 16Mx16 3.3V 54-Pin TSOP-II T/R

MT48LC16M16A2P-75 L:D TR

Manufacturer Part Number
MT48LC16M16A2P-75 L:D TR
Description
DRAM Chip SDRAM 256M-Bit 16Mx16 3.3V 54-Pin TSOP-II T/R
Manufacturer
Micron Technology Inc
Type
SDRAMr

Specifications of MT48LC16M16A2P-75 L:D TR

Package
54TSOP-II
Density
256 Mb
Address Bus Width
15 Bit
Operating Supply Voltage
3.3 V
Maximum Clock Rate
133 MHz
Maximum Random Access Time
6|5.4 ns
Operating Temperature
0 to 70 °C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
256M (16Mx16)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Package / Case
54-TSOP II
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1191-2
Command
Figure 47: WRITE With Auto Precharge
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
BA0, BA1
Address
DQM
CKE
A10
CLK
DQ
t CMS
t CKS
t AS
t AS
t AS
ACTIVE
Row
Row
Bank
T0
t CKH
t CMH
t AH
t AH
t AH
t RCD
t RAS
t RC
t CK
Note:
T1
NOP
Enable auto precharge
1. For this example, BL = 4.
t CMS
t CL
Column m
t DS
Bank
WRITE
T2
D
t CMH
IN
t CH
t DH
t DS
T3
NOP
D
IN
t DH
t DS
T4
NOP
D
IN
t DH
77
t DS
T5
NOP
D
IN
t DH
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t WR
T6
NOP
256Mb: x4, x8, x16 SDRAM
PRECHARGE Operation
NOP
T7
© 1999 Micron Technology, Inc. All rights reserved.
t RP
NOP
T8
Bank
Row
Row
ACTIVE
T9
Don’t Care

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