XA3S500E-4PQG208Q Xilinx Inc, XA3S500E-4PQG208Q Datasheet - Page 15

• Manufacturer Part Number: XA3S500E-4PQG208Q
• Description: FPGA XA Spartan™-3E Family 500K Gates 10476 Cells 572MHz 90nm Technology 1.2V 208-Pin PQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3E XAr

Specifications of XA3S500E-4PQG208Q

• Package: 208PQFP
• Family Name: XA Spartan™-3E
• Device Logic Units: 10476
• Device System Gates: 500000
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 158
• Ram Bits: 368640
• Number Of Logic Elements/cells: 10476
• Number Of Labs/clbs: 1164
• Total Ram Bits: 368640
• Number Of I /o: 158
• Number Of Gates: 500000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 14: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous)
DS635 (v2.0) September 9, 2009
Product Specification
Notes:
1.
2.
3.
4.
Setup Times
T
T
Hold Times
T
T
PSDCM
PSFD
PHDCM
PHFD
Symbol
The numbers in this table are tested using the methodology presented in
Table 6
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from
appropriate Input adjustment from the same table.
This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from
the appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s
active edge.
DCM output jitter is included in all measurements.
and
R
When writing to the Input Flip-Flop
(IFF), the time from the setup of
data at the Input pin to the active
transition at a Global Clock pin.
The DCM is used. No Input Delay
is programmed.
When writing to IFF, the time from
the setup of data at the Input pin to
an active transition at the Global
Clock pin. The DCM is not used.
The Input Delay is programmed.
When writing to IFF, the time from
the active transition at the Global
Clock pin to the point when data
must be held at the Input pin. The
DCM is used. No Input Delay is
programmed.
When writing to IFF, the time from
the active transition at the Global
Clock pin to the point when data
must be held at the Input pin. The
DCM is not used. The Input Delay
is programmed.
Table
9.
Description
LVCMOS25
IFD_DELAY_VALUE = 0,
with DCM
LVCMOS25
IFD_DELAY_VALUE =
default software setting
LVCMOS25
IFD_DELAY_VALUE = 0,
with DCM
LVCMOS25
IFD_DELAY_VALUE =
default software setting
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Conditions
(4)
(4)
(2)
(2)
(3)
(3)
,
,
,
,
Table 19
and are based on the operating conditions set forth in
VALUE=
DELAY_
IFD_
Table
0
2
3
2
5
4
0
2
3
2
5
4
Table
17. If this is true of the data Input, add the
17. If this is true of the data Input, subtract
XA3S100E
XA3S250E
XA3S500E
XA3S1200E
XA3S1600E
XA3S100E
XA3S250E
XA3S500E
XA3S1200E
XA3S1600E
XA3S100E
XA3S250E
XA3S500E
XA3S1200E
XA3S1600E
XA3S100E
XA3S250E
XA3S500E
XA3S1200E
XA3S1600E
Device
-4 Speed
Grade
–0.52
–0.24
–0.32
–0.49
–0.63
–0.39
2.98
2.59
2.59
2.58
2.59
3.58
3.91
4.02
5.52
4.46
0.14
0.14
0.15
0.14
Min
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15