XA3S500E-4PQG208Q Xilinx Inc, XA3S500E-4PQG208Q Datasheet - Page 23

• Manufacturer Part Number: XA3S500E-4PQG208Q
• Description: FPGA XA Spartan™-3E Family 500K Gates 10476 Cells 572MHz 90nm Technology 1.2V 208-Pin PQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3E XAr

Specifications of XA3S500E-4PQG208Q

• Package: 208PQFP
• Family Name: XA Spartan™-3E
• Device Logic Units: 10476
• Device System Gates: 500000
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 158
• Ram Bits: 368640
• Number Of Logic Elements/cells: 10476
• Number Of Labs/clbs: 1164
• Total Ram Bits: 368640
• Number Of I /o: 158
• Number Of Gates: 500000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 24: 18 x 18 Embedded Multiplier Timing (Continued)
Block RAM Timing
Table 25: Block RAM Timing
DS635 (v2.0) September 9, 2009
Product Specification
Notes:
1.
2.
3.
Clock Frequency
F
Clock-to-Output Times
T
Setup Times
T
T
T
T
Hold Times
T
T
T
T
MULT
BCKO
BACK
BDCK
BECK
BWCK
BCKA
BCKD
BCKE
BCKW
Symbol
Symbol
Combinatorial delay is less and pipelined performance is higher when multiplying input data with less than 18 bits.
The PREG register is typically used in both single-stage and two-stage pipelined multiplier implementations.
Input registers AREG or BREG are typically used when inferring a two-stage multiplier.
R
When reading from block RAM, the delay from the active transition
at the CLK input to data appearing at the DOUT output
Setup time for the ADDR inputs before the active transition at the
CLK input of the block RAM
Setup time for data at the DIN inputs before the active transition at
the CLK input of the block RAM
Setup time for the EN input before the active transition at the CLK
input of the block RAM
Setup time for the WE input before the active transition at the CLK
input of the block RAM
Hold time on the ADDR inputs after the active transition at the CLK
input
Hold time on the DIN inputs after the active transition at the CLK
input
Hold time on the EN input after the active transition at the CLK input
Hold time on the WE input after the active transition at the CLK input
Internal operating frequency for a two-stage 18x18 multiplier using the
AREG and BREG input registers and the PREG output register
Description
Description
www.xilinx.com
(1)
0.38
0.23
0.77
1.26
0.14
0.13
Min
-4 Speed Grade
0
0
-
-4 Speed Grade
Min
0
Max
2.82
-
-
-
-
-
-
-
-
Max
240
Units
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
23