XA3S500E-4PQG208Q Xilinx Inc, XA3S500E-4PQG208Q Datasheet - Page 26

• Manufacturer Part Number: XA3S500E-4PQG208Q
• Description: FPGA XA Spartan™-3E Family 500K Gates 10476 Cells 572MHz 90nm Technology 1.2V 208-Pin PQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3E XAr

Specifications of XA3S500E-4PQG208Q

• Package: 208PQFP
• Family Name: XA Spartan™-3E
• Device Logic Units: 10476
• Device System Gates: 500000
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 158
• Ram Bits: 368640
• Number Of Logic Elements/cells: 10476
• Number Of Labs/clbs: 1164
• Total Ram Bits: 368640
• Number Of I /o: 158
• Number Of Gates: 500000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 27: Switching Characteristics for the DLL (Continued)
Notes:
1.
2.
3.
4.
Digital Frequency Synthesizer
Table 28: Recommended Operating Conditions for the DFS
DS635 (v2.0) September 9, 2009
Product Specification
Notes:
1.
2.
3.
4.
Duty Cycle
CLKOUT_DUTY_CYCLE_DLL
Phase Alignment
CLKIN_CLKFB_PHASE
CLKOUT_PHASE_DLL
Lock Time
LOCK_DLL
Delay Lines
DCM_DELAY_STEP
Input Frequency Ranges
F
Input Clock Jitter Tolerance
CLKIN_CYC_JITT_FX_LF
CLKIN_CYC_JITT_FX_HF
CLKIN_PER_JITT_FX
CLKIN
The numbers in this table are based on the operating conditions set forth in
Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input.
For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. Example: The data sheet specifies a maximum
jitter of “±[1% of CLKIN period + 150]”. Assume the CLKIN frequency is 100 MHz. The equivalent CLKIN period is 10 ns and 1% of
10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 150 ps] = ±250ps.
DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are used.
If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in
CLKIN input jitter beyond these limits may cause the DCM to lose lock.
To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming
clock frequency by two as it enters the DCM.
(4)
(3)
Symbol
R
CLKIN_FREQ_FX
Symbol
(4)
(2)
(3)
Duty cycle variation for the CLK0, CLK90, CLK180,
CLK270, CLK2X, CLK2X180, and CLKDV outputs,
including the BUFGMUX and clock tree duty-cycle
distortion
Phase offset between the CLKIN and CLKFB inputs
Phase offset between DLL outputs
When using the DLL alone: The time
from deassertion at the DCM’s Reset
input to the rising transition at its
LOCKED output. When the DCM is
locked, the CLKIN and CLKFB
signals are in phase
Finest delay resolution
Frequency for the CLKIN input
Cycle-to-cycle jitter at the CLKIN
input, based on CLKFX output
frequency
Period jitter at the CLKIN input
Description
www.xilinx.com
Description
CLK0 to CLK2X
(not CLK2X180)
All others
5 MHz < F
F
CLKIN
15 MHz
F
F
Table 6
> 15 MHz
CLKFX
CLKFX
CLKIN
< 150 MHz
> 150 MHz
and
<
Table
Min
26.
20
-
-
-
-
-
-
-4 Speed Grade
0.200
-4 Speed Grade
Min
CLKIN period
CLKIN period
CLKIN period
-
-
-
±[1% of
±[1% of
±[1% of
+ 400]
+ 100]
+ 200]
±200
Max
600
40
5
333
±300
±150
Max
±1
Table
(4)
26.
Units
ms
ps
ps
ps
ps
μs
ps
Units
MHz
ps
ps
ns
26