XA3S500E-4PQG208Q Xilinx Inc, XA3S500E-4PQG208Q Datasheet - Page 31
![FPGA XA Spartan™-3E Family 500K Gates 10476 Cells 572MHz 90nm Technology 1.2V 208-Pin PQFP](/photos/6/71/67100/pq208_sml.jpg)
XA3S500E-4PQG208Q
Manufacturer Part Number
XA3S500E-4PQG208Q
Description
FPGA XA Spartan™-3E Family 500K Gates 10476 Cells 572MHz 90nm Technology 1.2V 208-Pin PQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3E XAr
Datasheet
1.XA3S100E-4VQG100I.pdf
(37 pages)
Specifications of XA3S500E-4PQG208Q
Package
208PQFP
Family Name
XA SpartanÂ-3E
Device Logic Units
10476
Device System Gates
500000
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
158
Ram Bits
368640
Number Of Logic Elements/cells
10476
Number Of Labs/clbs
1164
Total Ram Bits
368640
Number Of I /o
158
Number Of Gates
500000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 125°C
Package / Case
208-BFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XA3S500E-4PQG208Q
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XA3S500E-4PQG208Q
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Master Serial and Slave Serial Mode Timing
Table 38: Timing for the Master Serial and Slave Serial Configuration Modes
DS635 (v2.0) September 9, 2009
Product Specification
Notes:
1.
2.
Clock-to-Output Times
T
Setup Times
T
Hold Times
T
Clock Timing
T
T
F
Symbol
CCO
DCC
CCD
CCH
CCL
CCSER
The numbers in this table are based on the operating conditions set forth in
For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.
R
The time from the falling transition on the CCLK pin to data
appearing at the DOUT pin
The time from the setup of data at the DIN pin to the active edge of
the CCLK pin
The time from the active edge of the CCLK pin to the point when
data is last held at the DIN pin
High pulse width at the CCLK input pin
Low pulse width at the CCLK input pin
Frequency of the clock signal at
the CCLK input pin
Description
No bitstream compression
With bitstream compression
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Table
6.
Master
Master
Master
Slave/
Slave
Slave
Slave
Both
Both
Both
-4 Speed Grade
11.0
Min
1.5
0
0
0
See
See
See
See
Table 36
Table 37
Table 36
Table 37
66
Max
10.0
20
-
-
(2)
Units
MHz
MHz
ns
ns
ns
31