XA3S500E-4PQG208Q Xilinx Inc, XA3S500E-4PQG208Q Datasheet - Page 18

• Manufacturer Part Number: XA3S500E-4PQG208Q
• Description: FPGA XA Spartan™-3E Family 500K Gates 10476 Cells 572MHz 90nm Technology 1.2V 208-Pin PQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3E XAr

Specifications of XA3S500E-4PQG208Q

• Package: 208PQFP
• Family Name: XA Spartan™-3E
• Device Logic Units: 10476
• Device System Gates: 500000
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 158
• Ram Bits: 368640
• Number Of Logic Elements/cells: 10476
• Number Of Labs/clbs: 1164
• Total Ram Bits: 368640
• Number Of I /o: 158
• Number Of Gates: 500000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 18:
DS635 (v2.0) September 9, 2009
Product Specification
Single-Ended Standards
LVTTL
LVCMOS33
LVCMOS25
LVCMOS25 with 12mA Drive and
Signal Standard (IOSTANDARD)
Fast Slew Rate to the Following
Convert Output Time from
Output Timing Adjustments for IOB
R
Slow
Slow
Slow
Fast
Fast
Fast
12 mA
16 mA
12 mA
16 mA
12 mA
16 mA
12 mA
16 mA
12 mA
12 mA
2 mA
2 mA
2 mA
2 mA
4 mA
6 mA
8 mA
4 mA
6 mA
8 mA
2 mA
4 mA
6 mA
8 mA
4 mA
6 mA
8 mA
2 mA
4 mA
6 mA
8 mA
4 mA
6 mA
8 mA
Adjustment
-4 Speed
Add the
Below
Grade
5.41
2.41
1.90
0.67
0.70
0.43
5.00
1.96
1.45
0.34
0.30
0.30
5.29
1.89
1.04
0.69
0.42
0.43
4.87
1.52
0.39
0.34
0.30
0.30
4.21
2.26
1.52
1.08
0.68
3.67
1.72
0.46
0.21
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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Table 18:
Notes:
1.
2.
LVCMOS18
LVCMOS15
LVCMOS12
HSTL_I_18
HSTL_III_18
PCI33_3
SSTL18_I
SSTL2_I
Differential Standards
LVDS_25
BLVDS_25
MINI_LVDS_25
LVPECL_25
RSDS_25
DIFF_HSTL_I_18
DIFF_HSTL_III_18
DIFF_SSTL18_I
DIFF_SSTL2_I
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD)
The numbers in this table are tested using the methodology
presented in
set forth in
These adjustments are used to convert output- and
three-state-path times originally specified for the LVCMOS25
standard with 12 mA drive and Fast slew rate to times that
correspond to other signal standards. Do not adjust times that
measure when outputs go into a high-impedance state.
Convert Output Time from
Output Timing Adjustments for IOB
Table
Table 19
Slow
Slow
Slow
Fast
Fast
Fast
6,
Table
and are based on the operating conditions
9, and
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
6 mA
2 mA
4 mA
6 mA
2 mA
2 mA
Table
Adjustment
11.
Input Only
-4 Speed
Add the
Below
Grade
–0.20
–0.55
–0.56
–0.48
5.24
4.68
6.63
0.34
0.25
0.04
0.42
0.55
0.40
3.21
2.49
1.90
4.15
2.13
1.14
0.75
3.97
3.11
3.38
2.70
1.53
4.44
0.55
0.46
0.44
(Continued)
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
18