XA3S500E-4PQG208Q Xilinx Inc, XA3S500E-4PQG208Q Datasheet - Page 36

• Manufacturer Part Number: XA3S500E-4PQG208Q
• Description: FPGA XA Spartan™-3E Family 500K Gates 10476 Cells 572MHz 90nm Technology 1.2V 208-Pin PQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3E XAr

Specifications of XA3S500E-4PQG208Q

• Package: 208PQFP
• Family Name: XA Spartan™-3E
• Device Logic Units: 10476
• Device System Gates: 500000
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 158
• Ram Bits: 368640
• Number Of Logic Elements/cells: 10476
• Number Of Labs/clbs: 1164
• Total Ram Bits: 368640
• Number Of I /o: 158
• Number Of Gates: 500000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision History
The following table shows the revision history for this document.
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
DS635 (v2.0) September 9, 2009
Product Specification
08/31/07
01/20/09
09/09/09
Date
R
Version
1.0
1.1
2.0
Initial Xilinx release.
• Updated
• Updated T
• Updated description of T
• Removed Table 45: MultiBoot Trigger Timing.
• Added package sizes to
• Removed Genealogy Viewer Link from
• Updated data and notes for
• Updated test conditions for R
• Updated notes for
• Updated Max V
• Removed PCIX data, revised note 2, and added note 4 in
• Updated figure description of
• Added note 4 to
• Removed PC166_3 and PCIX adjustment values from
• Deleted Table 18 (duplicate of
• Removed PCIX data
• Removed PCIX data and removed V
• Updated T
• Updated notes, references to notes, and revised the maximum clock-to-output times for
• Added
• Updated note 3 in
• Added note 4
• Updated notes, references to notes, and CLKOUT_PER_JITT_FX data in
• Updated MAX_STEPS data in
• Updated ConfigRate Setting for T
• Updated ConfigRate Setting for F
LVCMOS18, LVCMOS15, and LVCMOS12, updated V
note 6 in
DIFF_HSTL_III_18, DIFF_SSTL18_I, and DIFF_SSTL2_I from
T
page
page
page
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27.
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30.
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"Key Feature Differences from Commercial XC Devices."
Table 9, page
ACC
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Table 24, page
Table 28, page
requirement in
CCO
minimum setup time in
Table 13, page
Table 8, page
Table 26, page
for LVTTL and LVCMOS33, removed PCIX data, updated V
www.xilinx.com
Table 18, page
11.
Table 2, page
DCC
22.
Table 6, page
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and T
Figure 5, page
26.
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Table 17, page
Table 31, page
14.
and maximum value for C
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24.
CCLK1
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CCD
43.
REF
18.
Revision
4.
Table 20, page
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in
to indicate 1 is the default value in
to indicate 1 is the default value in
values for DIFF_HSTL_I_18,
Table
8.
14.
17). Subsequent tables renumbered.
28.
42.
IH
20.
Table 17, page
Min for LVCMOS12, and added
IN
Table 10, page
in
Table 7, page
Table 19, page
5.
17.
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Table 29,
Table 34,
Table 35,
8.
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19.
Max for
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