XA3S500E-4PQG208Q Xilinx Inc, XA3S500E-4PQG208Q Datasheet - Page 3

• Manufacturer Part Number: XA3S500E-4PQG208Q
• Description: FPGA XA Spartan™-3E Family 500K Gates 10476 Cells 572MHz 90nm Technology 1.2V 208-Pin PQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3E XAr

Specifications of XA3S500E-4PQG208Q

• Package: 208PQFP
• Family Name: XA Spartan™-3E
• Device Logic Units: 10476
• Device System Gates: 500000
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 158
• Ram Bits: 368640
• Number Of Logic Elements/cells: 10476
• Number Of Labs/clbs: 1164
• Total Ram Bits: 368640
• Number Of I /o: 158
• Number Of Gates: 500000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Configuration
XA Spartan-3E FPGAs are programmed by loading config-
uration data into robust, reprogrammable, static CMOS con-
figuration latches (CCLs) that collectively control all
functional elements and routing resources. The FPGA’s
configuration data is stored externally in a PROM or some
other non-volatile medium, either on or off the board. After
applying power, the configuration data is written to the
FPGA using any of five different modes:
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DS635 (v2.0) September 9, 2009
Product Specification
Serial Peripheral Interface (SPI) from an
industry-standard SPI serial Flash
Byte Peripheral Interface (BPI) Up or Down from an
industry-standard x8 or x8/x16 parallel NOR Flash
Slave Serial, typically downloaded from a processor
Slave Parallel, typically downloaded from a processor
Boundary Scan (JTAG), typically downloaded from a
processor or system tester.
R
Notes:
1.
The XA3S1200E and XA3S1600E have two additional DCMs on both the left and right sides as
indicated by the dashed lines. The XA3S100E has only one DCM at the top and one at the bottom.
Figure 1: XA Spartan-3E Family Architecture
www.xilinx.com
I/O Capabilities
The XA Spartan-3E FPGA SelectIO interface supports
many popular single-ended and differential standards.
Table 2
ber of differential I/O pairs available for each device/pack-
age combination.
XA Spartan-3E FPGAs support the following single-ended
standards:
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3.3V low-voltage TTL (LVTTL)
Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,
1.5V, or 1.2V
3V PCI at 33 MHz
HSTL I and III at 1.8V, commonly used in memory
applications
SSTL I at 1.8V and 2.5V, commonly used for memory
applications
shows the number of user I/Os as well as the num-
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