LFE2M20E-6FN484C LATTICE SEMICONDUCTOR, LFE2M20E-6FN484C Datasheet - Page 127

• Manufacturer Part Number: LFE2M20E-6FN484C
• Description: FPGA LatticeECP2M Family 19000 Cells 90nm (CMOS) Technology 1.2V 484-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFE2M20E-6FN484C

• Package: 484FBGA
• Family Name: LatticeECP2M
• Device Logic Units: 19000
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 304
• Ram Bits: 1246208

Lattice Semiconductor
LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 144 TQFP (Cont.)
Number
Pin
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
91
92
93
94
95
96
97
98
99
RLM0_PLLCAP
Function
Pin/Pad
VCCIO2
VCCIO1
PR20B
PR20A
PR17B
PR17A
PR16B
PR16A
PR15B
PR15A
PR13B
PR13A
PT28B
PT28A
PT26B
PT26A
PT24B
PT24A
PT22B
PT22A
PT20B
PT20A
PT18B
PT18A
PT16A
PT14B
PT14A
PT12B
PT12A
PT10B
PT10A
XRES
PR2B
PR2A
GND
GND
GND
GND
VCC
VCC
VCC
VCC
NC
NC
Bank
LFE2-6E/SE
3
3
3
3
3
3
3
3
3
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
-
-
-
-
-
-
-
-
RLM0_GPLLC_IN_A**
RLM0_GDLLC_IN_A**
RLM0_GDLLT_IN_A**
RLM0_GPLLT_IN_A**
PCLKC2_0/RDQ10
PCLKT2_0/RDQ10
Dual Function
PCLKC3_0
PCLKT3_0
PCLKC1_0
PCLKT1_0
PCLKC0_0
PCLKT0_0
VREF2_3
VREF1_3
VREF1_2
VREF2_1
VREF1_1
VREF2_2
Differential
C (LVDS)*
T (LVDS)*
C (LVDS)*
T (LVDS)*
C (LVDS)*
C (LVDS)*
T (LVDS)*
T (LVDS)*
4-24
C
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
T
T
RLM0_PLLCAP
Function
Pin/Pad
VCCIO2
VCCIO1
PR20B
PR20A
PR17B
PR17A
PR16B
PR16A
PR15B
PR15A
PR13B
PR13A
PT55B
PT55A
PT54B
PT54A
PT52B
PT52A
PT50B
PT50A
PT48B
PT48A
PT44B
PT44A
PT40B
PT40A
PT34B
PT34A
PT30B
PT30A
PT28B
PT28A
XRES
PR2B
PR2A
GND
GND
GND
GND
VCC
VCC
VCC
VCC
NC
LatticeECP2/M Family Data Sheet
Bank
3
3
3
3
3
3
3
3
3
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
-
-
-
-
-
-
-
-
LFE2-12E/12SE
RLM0_GPLLC_IN_A**
RLM0_GDLLC_IN_A**
RLM0_GDLLT_IN_A**
RLM0_GPLLT_IN_A**
PCLKC2_0/RDQ10
PCLKT2_0/RDQ10
PCLKC3_0
PCLKC1_0
PCLKC0_0
PCLKT3_0
PCLKT1_0
PCLKT0_0
Function
VREF2_3
VREF1_3
VREF2_2
VREF1_2
VREF2_1
VREF1_1
Dual
Pinout Information
Differential
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
C
C
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
T
T
T