PSB50505EV13GXT Lantiq, PSB50505EV13GXT Datasheet - Page 124
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PSB50505EV13GXT
Manufacturer Part Number
PSB50505EV13GXT
Description
Manufacturer
Lantiq
Datasheet
1.PSB50505EV13GXT.pdf
(290 pages)
Specifications of PSB50505EV13GXT
Lead Free Status / RoHS Status
Supplier Unconfirmed
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next_slot_nr Next slot number
sdt_mfs
sig_cond
srts
subst_
bpslct
dcor
dcor_
random_nr
aal0
part_fill
Data Sheet
If band_width > 0 next_slot_nr points to the next slot of this channel.
If band_width = 0 and CAS is activated next_slot_nr[3:0] will be used as
signalling conditioning nibbles.
If band_width = 0 and CAS is not activated next_slot_nr is don’t care.
SDT multiframe pulse select
X =
0 =
1 =
Signalling conditioning upstream
0 =
1 =
SRTS enable
Enables RTS value insertion into AAL1 SAR-PDUs
X =
0 =
1 =
Substitute byte-pattern select
00 =
01 =
10 =
11 =
Decorrelation circuit enable
0 =
1 =
Decorrelation random Number
X =
AAL0 enable
0 =
1 =
Partially filled cell filling level
If [aal0] = 1 or [sdt] = 0 or pcfN[p_ces] = 1
Start of structure is frame pulse
Start of structure is multiframe pulse as defined by
pcfN[p_tx_mfs]
CAS freezing upstream enabled in "loss of signal" condition
CAS conditioning upstream enabled in "loss of signal" condition
If pcfN[p_srts] = 0 or [aal0] = 1
Disabled
Enabled
Select byte-pattern 0, defined in bp10[bp0]
Select byte-pattern 1, defined in bp10[bp1]
Select byte-pattern 2, defined in bp32[bp2]
Select byte-pattern 3, defined in bp32[bp3]
Disabled
Enabled
if [dcor] = 0
Disabled (AAL1 is used)
Enabled (instead of AAL1)
124
PXB 4219E, PXB 4220E, PXB 4221E
Memory Structure
IWE8, V3.4
2003-01-20
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