PSB50505EV13GXT Lantiq, PSB50505EV13GXT Datasheet - Page 156

• Manufacturer Part Number: PSB50505EV13GXT
• Manufacturer: Lantiq

Specifications of PSB50505EV13GXT

• Lead Free Status / RoHS Status: Supplier Unconfirmed

7.3
Read/write Address 00009
Reset value: 0000
tim_set1_en Timer set 1 enable
dest_read
oam_act
Data Sheet
15
7
OAM Control Register (oamc)
0 =
1 =
Destructive read mode
0 =
1 =
OAM active
0 =
1 =
H
Disabled
Enabled
Disabled
Enabled: OAM counter values in the external RAM are reset after
being read by the micro-processor.
(Only accepted if “oam_act” = 1)
The protocol monitoring is disabled and the microprocessor can
read and write the complete external RAM for test.
The protocol monitoring is enabled and the RAM arbiter grants
both the protocol monitoring and the microprocessor access to
the external RAM. Reading any address of Interrupt Queue by
the microprocessor always yields the first interrupt in the queue.
Not used
H
Not used
156
PXB 4219E, PXB 4220E, PXB 4221E
set1_en
tim_
Register Description
dest_
read
IWE8, V3.4
2003-01-20
oam_
act
8
0