PSB50505EV13GXT Lantiq, PSB50505EV13GXT Datasheet - Page 171

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PSB50505EV13GXT

Manufacturer Part Number
PSB50505EV13GXT
Description
Manufacturer
Lantiq
Datasheet

Specifications of PSB50505EV13GXT

Lead Free Status / RoHS Status
Supplier Unconfirmed
7.18
Read only, Address 00018
Reset value: 0000
iq_ne
eis4
eis3
eis2
eis1
eis0
ut_soc
Data Sheet
Not used
iq_ne
15
7
Interrupt Status Register 1 (isr1)
ut_soc
eis4
Interrupt queue not empty
0 =
1 =
A bit is set in eis4
0 =
1 =
A bit is set in eis3
0 =
1 =
A bit is set in eis2
0 =
1 =
A bit is set in eis1
0 =
1 =
A bit is set in eis0
0 =
1 =
UTOPIA start of cell error,
indicates if SOC is activated too late or twice within one cell cycle.
(corresponds to transmit direction in slave mode and receive direction in
master mode).
0 =
1 =
H
False
True
False
True
False
True
False
True
False
True
False
True
False
True
ut_par
eis3
H
ex_par
eis2
171
PXB 4219E, PXB 4220E, PXB 4221E
crv_par
eis1
oq_ovf
eis0
Register Description
eq_ovf
Not used
IWE8, V3.4
2003-01-20
ck_eme
8
0

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