PSB50505EV13GXT Lantiq, PSB50505EV13GXT Datasheet - Page 248

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PSB50505EV13GXT

Manufacturer Part Number
PSB50505EV13GXT
Description
Manufacturer
Lantiq
Datasheet

Specifications of PSB50505EV13GXT

Lead Free Status / RoHS Status
Supplier Unconfirmed
Table 34
No.
1A
2
2A
3
1)
2)
9.6.2
9.6.2.1
Framer Receive Interface
Figure 57
Data Sheet
RFCLK
FRCLK
FRFRS
FRDAT
FRMFB
The frequency should be equal or higher than RXCLK and TXCLK of the UTOPIA interface
Only required if the Internal Clock Recovery Circuit is used for SRTS
Parameter
F
GIM T1:
others:
T
F
Pulse width RESET low
CLOCK
CLK52
CLK52
Framer Interface
Framer Interface in FAM
Clock and Reset Interface AC Timing Characteristics (cont’d)
Framer Receive Interface Timing in FAM
: Period CLK52
: Frequency CLK52
: Frequency CLOCK
3
2)
1
2)
1)
3
4
248
6
PXB 4219E, PXB 4220E, PXB 4221E
Min
18,53
24,58
-50 ppm
-50 ppm
3xT
5
7
CLOCK
Limit Values
Typ
25
25
19.29
51.84
Electrical Characteristics
2
Max
38,88
38,88
+50 ppm ns
+50 ppm MHz
IWE8, V3.4
2003-01-20
FRITFAM
Unit
MHz
MHz

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