PSB50505EV13GXT Lantiq, PSB50505EV13GXT Datasheet - Page 257

• Manufacturer Part Number: PSB50505EV13GXT
• Manufacturer: Lantiq

Specifications of PSB50505EV13GXT

• Lead Free Status / RoHS Status: Supplier Unconfirmed

The setup and the hold times are defined with regard to a positive clock edge, see
Figure
Taking the actual used clock frequency into account (e.g. up to the max. frequency), the
corresponding (min. and max.) transmit side “clock to output” propagation delay
specifications can be derived. The timing references (tT5 to tT12) are according
toTable 42
In the following tables, A P (column DIR, Direction) defines a signal from the ATM layer
(transmitter, driver) to the PHY layer (receiver), A P defines a signal from the PHY layer
(transmitter, driver) to the ATM layer (receiver).
Figure 64
Figure 65
Data Sheet
Signal
Clock
Signal
Clock
64.
impedance from clock
to
Table
Setup and hold time definition (single- and multi PHY)
Tri-state timing (multi-PHY, multiple devices only)
signal going low
tT11
45.
input setup to clock input hold from clock
tT5, tT7
impedance to clock
signal going low
tT9
257
tT6, tT8
PXB 4219E, PXB 4220E, PXB 4221E
impedance from clock
signal going high
tT12
Electrical Characteristics
signal going high
impedance to clock
tT10
IWE8, V3.4
2003-01-20
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