PXB4219EV34NP Infineon Technologies, PXB4219EV34NP Datasheet - Page 79
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PXB4219EV34NP
Manufacturer Part Number
PXB4219EV34NP
Description
Manufacturer
Infineon Technologies
Datasheet
1.PXB4219EV34NP.pdf
(290 pages)
Specifications of PXB4219EV34NP
Data Rate
2.048Mbps
Number Of Channels
1
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
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4.6
4.6.1
All the functional blocks that process octets or cells can generate counter events, i.e.
commands to increment a particular counter in the external RAM. All counter events are
written in a FIFO queue that can store 256 counter events.
A counter event contains the statistics counter address in external RAM and an
increment value.
4.6.2
When a cell is completely stored in the ATM Receive or Segmentation Buffer, it is ready
to be transmitted to the ATM layer over the UTOPIA receive interface. The external RAM
address of the cell is stored in a common Output Queue (OQ).
The Output Queue is a First In First Out (FIFO) queue with a maximum of 256 cell
address entries. It is common to ATM and AAL mode ports.
As long as the Output Queue is not empty, the Cell Receive processing (CR) will write
the corresponding cell from external RAM to the UTOPIA Receive interface (UR).
4.6.3
The Interrupt Queue in external RAM is handled as a FIFO which is written whenever a
counter reaches its threshold value.
When there are interrupts in the Interrupt Queue, the “iq_ne” bit in the interrupt status
register 1 “isr1” will be set to 1. When the corresponding bit is not masked in the “imr1”
register an interrupt will be generated on the MPIR1 pin.
The microprocessor should react on the interrupt by reading the Interrupt Queue. When
“oam_act” is set to 1, the MPADR(12:1) address bits are don’t care. The next Interrupt
Queue entry will automatically be provided.
Each Interrupt Queue entry identifies a particular OAM counter that has reached its
threshold value. The counter is identified by its “port_nr”, “channel_nr” and “counter_nr”.
When the microprocessor reads the counter value and the “dest_read” bit of the register
oamc is set to 1, the counter is automatically reset.
Each Interrupt Queue entry also indicates whether there are still more interrupts in the
queue in the “iq_ne” field of the interrupt status register “isr1”. This allows the software
to read the Interrupt Queue until it is empty without having to read the interrupt status
register “isr1” again.
When the statistics function is disabled (oamc[oam_act] = 0), the P can read and write
all addresses of the Interrupt Queue.
Data Sheet
Internal Queues
Event Queue
Output Queue
Interrupt Queue
79
PXB 4219E, PXB 4220E, PXB 4221E
Operational Description
IWE8, V3.4
2003-01-20
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