LAN9115-MT Standard Microsystems (SMSC), LAN9115-MT Datasheet - Page 118

• Manufacturer Part Number: LAN9115-MT
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9115-MT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

Chapter 6 Timing Diagrams
Revision 1.5 (07-11-08)
6.1
6.1.1
Read Cycles:
Write Cycles:
The LAN9115 supports the following host cycles:
Special Restrictions on Back-to-Back Write/Read Cycles
It is important to note that there are specific restrictions on the timing of back-to-back write-read
operations. These restrictions concern reading the control registers after any write cycle to the
LAN9115 device. In many cases there is a required minimum delay between writing to the LAN9115,
and the subsequent side effect (change in the control register value). For example, when writing to the
TX Data FIFO, it takes up to 135ns for the level indication to change in the TX_FIFO_INF register.
In order to prevent the host from reading stale data after a write operation, minimum wait periods must
be enforced. These periods are specified in
processor is required to wait the specified period of time after any write to the LAN9115 before reading
the resource specified in the table. These wait periods are for read operations that immediately follow
any write cycle. Note that the required wait period is dependant upon the register being read after the
write.
Performing "dummy" reads of the BYTE_TEST register is a convenient way to guarantee that the
minimum write-to-read timing restriction is met.
are required before reading the register indicated. The number of BYTE_TEST reads in this table is
based on the minimum timing for Tcycle (165ns). For microprocessors with slower busses the number
of reads may be reduced as long as the total time is equal to, or greater than the time specified in the
table. Note that dummy reads of the BYTE_TEST register are not required as long as the minimum
time period is met.
Host Interface Timing
PIO Reads (nCS or nRD controlled)
PIO Burst Reads (nCS or nRD controlled)
RX Data FIFO Direct PIO Reads (nCS or nRD controlled)
RX Data FIFO Direct PIO Burst Reads (nCS or nRD controlled)
PIO writes (nCS and nWR controlled)
TX Data FIFO direct PIO writes (nCS or nWR controlled)
DATASHEET
118
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Table 6.1, "Read After Write Timing
Table 6.1
also shows the number of dummy reads that
Rules". The host
SMSC LAN9115
Datasheet