LAN9115-MT Standard Microsystems (SMSC), LAN9115-MT Datasheet - Page 83

• Manufacturer Part Number: LAN9115-MT
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9115-MT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9115
TX_FIF_SZ
10
12
13
14
11
2
3
4
5
6
7
8
9
RX FIFO Size = 16384 – 6144 = 10240 Bytes (10KB)
RX Status FIFO Size = 10240 / 16 = 640 Bytes (160 RX Status DWORDs)
RX Data FIFO Size = 10240 – 640 = 9600 Bytes
Table 5.3
are reserved and should not be used.
Note: The RX data FIFO is considered full 4 DWORDs before the length that is specified in the
In addition to the host-accessible FIFOs, the MAC Interface Layer (MIL) contains an additional 2K
bytes of TX, and 128 bytes of RX FIFO buffering. These sizes are fixed, and cannot be adjusted by
the host.
As space in the TX MIL (Mac Interface Layer) FIFO frees, data is moved into it from the TX data FIFO.
Depending on the size of the frames to be transmitted, the MIL can hold up to two Ethernet frames.
This is in addition to any TX data that may be queued in the TX data FIFO.
Conversely, as data is received by the LAN9115, it is moved from the MAC to the RX MIL FIFO, and
then into the RX data FIFO. When the RX data FIFO fills up, data will continue to collect in the RX
MIL FIFO. If the RX MIL FIFO fills up and overruns, subsequent RX frames will be lost until room is
made in the RX data FIFO. For each frame of data that is lost, the RX Dropped Frames Counter
(RX_DROP) is incremented.
RX and TX MIL FIFO levels are not visible to the host processor. RX and TX MIL FIFOs operate
independent of the TX adatand RX data and status FIFOs. FIFO levels set for the RX and TX data
and Status FIFOs do not take into consideration the MIL FIFOs.
HW_CFG register.
shows every valid setting for the TX_FIF_SZ field. Note that settings not shown in this table
TX DATA FIFO
SIZE (BYTES)
10752
12800
13824
11776
1536
2560
3584
4608
5632
6656
7680
8704
9728
Table 5.3 Valid TX/RX FIFO Allocations
TX STATUS FIFO
DATASHEET
SIZE (BYTES)
512
512
512
512
512
512
512
512
512
512
512
512
512
83
RX DATA FIFO
SIZE (BYTES)
13440
12480
11520
10560
9600
8640
7680
6720
5760
4800
3840
2880
1920
RX STATUS FIFO
Revision 1.5 (07-11-08)
SIZE (BYTES)
896
832
768
704
640
576
512
448
384
320
256
192
128