LAN9115-MT Standard Microsystems (SMSC), LAN9115-MT Datasheet - Page 121
![no-image](/images/manufacturer_photos/0/6/632/standard_microsystems__smsc__sml.jpg)
LAN9115-MT
Manufacturer Part Number
LAN9115-MT
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.LAN9115-MT.pdf
(136 pages)
Specifications of LAN9115-MT
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
2.97V
Operating Supply Voltage (max)
3.63V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LAN9115-MT
Manufacturer:
Standard
Quantity:
1 907
Company:
Part Number:
LAN9115-MT
Manufacturer:
SMSC
Quantity:
672
Company:
Part Number:
LAN9115-MT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
LAN9115-MT
Manufacturer:
SMSC
Quantity:
20 000
Company:
Part Number:
LAN9115-MT-E2
Manufacturer:
SMSC
Quantity:
3 994
Part Number:
LAN9115-MT-E2
Manufacturer:
SMSC
Quantity:
20 000
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9115
6.2
SYMBOL
t
t
cycle
t
t
t
t
t
csdv
t
t
asu
don
doff
doh
csh
nCS, nRD
csl
ah
A[7:1]
Data Bus
PIO reads can be used to access CSRs or RX Data and RX/TX status FIFOs. In this mode, counters
in the CSRs are latched at the beginning of the read cycle. Read data is valid as indicated in the timing
diagram. PIO reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both
of these control signals must go high between cycles for the period specified.
Note: Some registers have restrictions on the timing of back-to-back, write-read and read-read
Note: The “Data Bus” width is 16 bits
Note: A PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either
PIO Reads
DESCRIPTION
Read Cycle Time
nCS, nRD Assertion Time
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address Setup to nCS, nRD Valid
Address Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
cycles.
or both nCS and nRD are deasserted. They may be asserted and deasserted in any order.
Figure 6.1 LAN9115 PIO Read Cycle Timing
Table 6.3 PIO Read Timing
DATASHEET
121
MIN
165
32
13
0
0
0
0
TYP
Revision 1.5 (07-11-08)
MAX
30
7
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns