LAN9420-NU Standard Microsystems (SMSC), LAN9420-NU Datasheet - Page 23

• Manufacturer Part Number: LAN9420-NU
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9420-NU

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
Chapter 3 Functional Description
SMSC LAN9420/LAN9420i
3.1
3.2
Functional Overview
PCI Bridge (PCIB)
The LAN9420/LAN9420i Ethernet Controller consists of five major functional blocks. These blocks are:
The following sections discuss the features of each block. A block diagram of LAN9420/LAN9420i is
shown in
The PCI Bridge (PCIB) facilitates LAN9420/LAN9420i’s operation on a PCI bus as a device. It has the
following features:
PCI Master Interface: This interface connects LAN9420/LAN9420i to the PCI bus when it is
functioning as a PCI Master. It is used by the DMA engines to directly access the PCI Host’s memory.
PCI Target Interface: This interface connects LAN9420/LAN9420i to the PCI bus when it is functioning
as a PCI Target. It provides access to PCI Configuration Space Control and Status Register (CONFIG
CSR), and access to the Control and Status Registers (CSR) via I/O or Non-Prefetchable (NP) memory
accesses. In addition, Big/Little Endian support for the registers may be selected.
PCI Power Management Support: LAN9420/LAN9420i supports PCI Bus Power Management
Interface Specification Rev. 1.1. Refer to
information.
Interrupt Gating Logic: This logic controls assertion of the nINT signal to the Host system.
PCI Configuration Space Control and Status Registers (CONFIG CSR): The Host system controls
and monitors the LAN9420/LAN9420i device using registers in this space.
PCI Bridge (PCIB)
System Control Block (SCB)
DMA Controller (DMAC)
10/100 Ethernet MAC
10/100 Ethernet PHY
Figure 1.2 LAN9420/LAN9420i Internal Block Diagram on page
DATASHEET
23
Section 3.7, "Power Management," on page 73
11.
Revision 1.4 (12-17-08)
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