LAN9420-NU Standard Microsystems (SMSC), LAN9420-NU Datasheet - Page 32

• Manufacturer Part Number: LAN9420-NU
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9420-NU

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Revision 1.4 (12-17-08)
3.3.5.2
3.3.5.3
Subsystem ID [15:0]
Subsystem Vendor ID [15:0]
MAC Address [47:0]
Note: EEPROM byte addresses past 0Ah can be used to store data for any purpose.
The signature value of 0xA5 is stored at address 0. A different signature value indicates to the
EEPROM controller that no EEPROM or an un-programmed EEPROM is attached to
LAN9420/LAN9420i. In this case, following default values are used for the Subsystem Device ID
(SSID), Subsystem Vendor ID (SSVID), and the MAC address.
MAC Address, Subsystem ID, and Subsystem Vendor ID Auto-Load
On a system-level reset, the EEPROM controller attempts to read the first byte of data from the
EEPROM (address 00h). If the value A5h is read from the first address, then the EEPROM controller
will assume that an external EEPROM is present. The EEPROM controller will then access the next
EEPROM byte and send it to the MAC Address register byte 0 (ADDRL[7:0]). This process will be
repeated for the next five bytes of the MAC Address, thus fully programming the 48-bit MAC address.
The Subsystem ID and Subsystem Vendor ID are similarly extracted from the EEPROM and are used
to set the value of the analogous PCI Header registers contained within the PCIB. Once all eleven
bytes have been programmed, the “EEPROM Loaded” bit is set in the E2P_CMD register. A detailed
explanation of the EEPROM byte ordering with respect to the MAC address is given in
"MAC Address Low Register (ADDRL)," on page
If an 0xA5h is not read from the first address, the EEPROM controller will end initialization. The default
values, as specified in
responsibility of the Host LAN driver software to set the IEEE address by writing to the MAC’s ADDRH
and ADDRL registers.
EEPROM Host Operations
After the EEPROM controller has finished reading (or attempting to read) the EEPROM after a system-
level reset, the Host is free to perform other EEPROM operations. EEPROM operations are performed
using the EEPROM Command (E2P_CMD) and EEPROM Data (E2P_DATA) registers.
"EEPROM Command Register (E2P_CMD)," on page 99
EEPROM operations.
If the EEPROM operation is the “write location” (WRITE) or “write all” (WRAL) commands, the Host
must first write the desired data into the E2P_DATA register. The Host must then issue the WRITE or
WRAL command using the E2P_CMD register by setting the EPC_CMD field appropriately. If the
operation is a WRITE, the EPC_ADDR field in E2P_CMD must also be set to the desired location. The
command is executed when the Host sets the EPC_BSY bit high. The completion of the operation is
indicated when the EPC_BSY bit is cleared.
If the EEPROM operation is the “read location” (READ) operation, the Host must issue the READ
command using the E2P_CMD register with the EPC_ADDR set to the desired location. The command
is executed when the Host sets the EPC_BSY bit high. The completion of the operation is indicated
when the EPC_BSY bit is cleared, at which time the data from the EEPROM may be read from the
E2P_DATA register.
Other EEPROM operations are performed by writing the appropriate command to the E2P_CMD
register. The command is executed when the Host sets the EPC_BSY bit high. The completion of the
operation is indicated when the EPC_BSY bit is cleared. In all cases, the Host must wait for EPC_BSY
to clear before modifying the E2P_CMD register.
VARIABLE
Table
Table 3.3 EEPROM Variable Defaults
3.3, will then be assumed by the associated registers. It is then the
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
DATASHEET
32
0x9420
0x1055
0xFFFF_FFFF_FFFF
124.
provides an explanation of the supported
DEFAULT
SMSC LAN9420/LAN9420i
Section 4.2.11,
Section 4.4.3,
Datasheet