LAN9420-NU Standard Microsystems (SMSC), LAN9420-NU Datasheet - Page 45
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LAN9420-NU
Manufacturer Part Number
LAN9420-NU
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.LAN9420-NU.pdf
(170 pages)
Specifications of LAN9420-NU
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
128
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LAN9420-NU
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
LAN9420-NU
Manufacturer:
SMSC
Quantity:
20 000
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Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i
TDES0
TDES2
TDES3
TDES1
3.4.2.2
BITS
31:0
OW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC LS FS R
Receive Descriptor 3 (RDES3)
Transmit descriptors
The descriptors must be 4-DWORD (16-byte) aligned, while there are no alignment restrictions on
transmit buffer addresses. Providing two buffers, two byte-count buffers, and two address pointers in
each descriptor facilitates compatibility with various types of memory-management schemes.
Figure 3.17
Buffer 2 Address Pointer (Next Descriptor Address)
The RCH (Second Address Chained) bit (RDES1[24]) determines the usage of this field as
follows:
RCH is zero: This field contains the pointer to the address of buffer 2 in Host memory. The buffer
must be DWORD (32-bit) aligned (RDES3[1:0] = 00b). In the case where the buffer is not
DWORD aligned, the resulting behavior is undefined.
RCH is one: Descriptor chaining is in use and this field contains the pointer to the next descriptor
in Host memory. The descriptor must be 4-DWORD (16-byte) aligned (RDES3[3:0] = 0000b). In
the case where the buffer is not 4-DWORD aligned, the resulting behavior is undefined.
Note:
Host Actions: Initializes this field.
DMAC Actions: Reads this field upon opening a new DMA descriptor to obtain the buffer
address.
CK
shows the Transmit Descriptor format.
If RER (RDES1[25]) is set, RCH is ignored and this field is treated as a pointer to buffer
2 as in the “RCH is zero” case above.
AC TE TC DP R
RESERVED
Figure 3.17 Transmit Descriptor
Table 3.8 RDES3 Bit Fields
DATASHEET
BUFFER 1 ADDRESS POINTER
BUFFER 2 ADDRESS POINTER
45
DESCRIPTION
TBS2
ES
RES
LC NC LT EC HF
TBS1
Revision 1.4 (12-17-08)
CC
ED UE DE
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