LAN9420-NU Standard Microsystems (SMSC), LAN9420-NU Datasheet - Page 79

• Manufacturer Part Number: LAN9420-NU
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9420-NU

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i
3.7.5
(except PME registers)
PCI Configuration
PCI PME Logic
EEPROM Load
TX/RX DMACS
(Note
Registers
BLOCK
SCSR
MAC
PHY
Resets
The LAN9420/LAN9420i device employs the following resets:
The reset map in
LAN9420/LAN9420i are reset.
Note 3.6
Note 3.7
Note 3.8
Note 3.9
3.11)
Power-On Reset (POR): This reset is asserted on initial application of device power. If the device
is powered from the PCI auxiliary power supply, this reset is asserted for approximately 21mS after
3.3Vaux has reached its operational level. If the device is not powered from the auxiliary supply,
this reset is asserted for approximately 21mS after the main PCI 3.3V supply has reached its
operational level.
PCInRST: This is the active-low reset input from the PCI bus. In the D0
is reset when PCInRST is low. In the D3
deassertion (low-to-high transition) of PCInRST.
D3 Transition Reset (D3RST): This reset occurs when transitioning from the D3
Software Reset (SRST): This reset is initiated by setting the
Mode Register
PHY Reset via PMT_CTRL (PHY_RST): This reset is asserted by setting the
(PHY_RST)
3.6.9.1, "PHY Soft Reset via PMT_CTRL bit 10 (PHY_RST)," on page 73
PHY Soft Reset (PHY_SRST): This reset is asserted by writing a ‘1’ to bit 15 of the PHY’s Basic
Control Register. Refer to section
bit 15 (PHY Reg. 0.15)," on page 73
PME logic is reset by PCInRST if LAN9420/LAN9420i is not configured to support D3
wake; PME logic is not reset by PCInRST if LAN9420/LAN9420i is configured to support
D3
Software Reset does not clear control register bits marked as NASR.
If PHY was reset on entry to the D3
was not reset on entry to the D3
The
loaded from the EEPROM) are not reset during this transition.
COLD
in the
Subsystem Vendor ID (SSVID) Subsystem Device ID (SSID)
(BUS_MODE). Software Reset does not clear control register bits marked as NASR.
POR
wake.
Table 3.22
X
X
X
X
X
X
X
Power Management Control Register
PCInRST
Note 3.6
Table 3.22 Reset Map
shows the conditions under which various modules within
DATASHEET
X
X
X
X
X
X
Section 3.6.9.2, "PHY Soft Reset via PHY Basic Control Register
for more information.
79
HOT
HOT
(Note
Note 3.8
D3RST
HOT
, it will not be reset when exiting D3
or D3
X
X
X
X
, it will be reset when exiting the D3
3.9)
COLD
(Note
states, the device is reset on the
(PMT_CTRL). Refer to section
SRST
Software Reset (SRST)
X
X
X
3.7)
U
PHY_RST
or D0
for more information.
X
Revision 1.4 (12-17-08)
A
registers (optionally
PHY Reset
HOT
states, the device
HOT
HOT
to D0
bit in the
.
PHY_SRST
(Note
. If the PHY
Section
U
X
3.10)
states.
COLD
Bus