LAN9420-NU Standard Microsystems (SMSC), LAN9420-NU Datasheet - Page 67

• Manufacturer Part Number: LAN9420-NU
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9420-NU

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i
3.6.1.3
3.6.1.4
3.6.1.5
3.6.2
3.6.2.1
3.6.2.2
MAC
Converter
Converter
NRZI
NRZI and MLT3 Encoding
The scrambler block passes the 5-bit wide parallel data to the NRZI converter where it becomes a
serial 125MHz NRZI data stream. The NRZI is encoded to MLT-3. MLT3 is a tri-level code where a
change in the logic level represents a code bit “1” and the logic output remaining at the same level
represents a code bit “0”.
100M Transmit Driver
The MLT3 data is then passed to the analog transmitter, which launches the differential MLT-3 signal,
on outputs TPO+ and TPO-, to the twisted pair media via a 1:1 ratio isolation transformer. The
10BASE-T and 100BASE-TX signals pass through the same transformer so that common “magnetics”
can be used for both. The transmitter drives into the 100Ω impedance of the CAT-5 cable. Cable
termination and impedance matching require external components.
100M Phase Lock Loop (PLL)
The 100M PLL locks onto reference clock and generates the 125MHz clock used to drive the 125 MHz
logic and the 100BASE-Tx Transmitter.
100BASE-TX Receive
The receive data path is shown in
100M Receive Input
The MLT-3 from the cable is fed into the PHY (on inputs TPI+ and TPI-) via a 1:1 ratio transformer.
The ADC samples the incoming differential signal at a rate of 125M samples per second. Using a 64-
level quanitizer it generates 6 digital bits to represent each sample. The DSP adjusts the gain of the
ADC according to the observed signal levels such that the full dynamic range of the ADC can be used.
Equalizer, Baseline Wander Correction and Clock and Data Recovery
The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates
for phase and amplitude distortion caused by the physical channel consisting of magnetics, connectors,
A/D
MII 25MHz by 4 bits
RX_CLK
Internal
NRZI
MLT-3
Converter
MLT-3
Magnetics
100M
PLL
Figure 3.26 Receive Data Path
MII
MLT-3
DATASHEET
Figure
125 Mbps Serial
MLT-3
by 4 bits
25MHz
3.26. Detailed descriptions follow.
6 bit Data
67
RJ45
Decoder
4B/5B
and BLW Correction
recovery, Equalizer
MLT-3
DSP: Timing
25MHz by
CAT-5
5 bits
Descrambler
and SIPO
Revision 1.4 (12-17-08)