LAN9420-NU Standard Microsystems (SMSC), LAN9420-NU Datasheet - Page 38

• Manufacturer Part Number: LAN9420-NU
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9420-NU

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Revision 1.4 (12-17-08)
3.3.6
3.4
3.4.1
3.4.2
DMA Controller (DMAC)
System Control and Status Registers (SCSR)
Please refer to
description of the SCSR.
The DMA Controller is designed to transfer data from and to the MAC RX and TX Data paths. Similar
to the MAC, it contains separate TX and RX data paths that are controlled by a single arbiter.
The DMA Controller includes the following features:
The DMA controller consists of independent transmit (TX) and receive (RX) engines and a control and
status register space (DCSR). The transmit engine transfers data from Host memory through the PCI
Bridge (PCIB) to the MAC, while the receive engine transfers data from the MAC, through the PCIB
to Host memory. The DMAC utilizes descriptors to efficiently move data from source to destination with
minimal Host intervention. Descriptors are 4-DWORD (16-byte) aligned data structures in Host memory
that inform the DMAC of the location of data buffers in Host memory and also provide a mechanism
for communicating status to the Host on completion of DMA transactions. The DMAC has been
designed for packet-oriented data transfer, such as frames in Ethernet. The DMAC can be programmed
to assert an interrupt for situations such as frame transmit or receive transfer completed, and other
normal, as well as error conditions that are described in the DMAC Control and Status Registers
(DCSR) section.
Note: Descriptors should not cross cache line boundaries if cache memory is used.
DMA Controller Architecture
The DMA Controller has four main hardware components: TX DMA engine, RX DMA engine, the DMA
arbiter, and the DCSR.
Data Descriptors and Buffers
The DMAC and the driver communicate through two data structures:
Generic 32-bit DMA with single-channel Transmit and Receive engines
Optimized for packet-oriented DMA transfers with frame delimiters
Supports dual-buffer and linked-list Descriptor Chaining
Descriptor architecture allows large blocks of data transfer with minimum Host intervention - each
descriptor can transfer up to 2KB of data
Comprehensive status reporting for normal operation and transfers with errors
Supports programmable interrupt options for different operational conditions
Supports Start/Stop modes of operation
Selectable round-robin or fixed priority arbitration between Receive and Transmit engines
TX DMA Engine - The transmit DMA engine fetches transmit descriptors from Host memory and
handles data transfers from Host memory to the MAC destination port.
RX DMA Engine - The receive DMA engine fetches receive descriptors from Host memory and
handles data transfers from the MAC source port to destination buffers in Host memory.
DMA Arbiter - The DMA arbiter controls access to Host memory. It can be configured to support
round robin or fixed priority arbitration.
DCSR - The DMA control and status register block implements register bits that control and monitor
the operation of the DMA subsystem.
DMA Control and Status Registers (DCSR), as described in
Registers (DCSR)," on page
Section 4.2, "System Control and Status Registers (SCSR)," on page 86
103.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
DATASHEET
38
Section 4.3, "DMAC Control and Status
SMSC LAN9420/LAN9420i
for a complete
Datasheet