LAN9420-NU Standard Microsystems (SMSC), LAN9420-NU Datasheet - Page 92
![no-image](/images/manufacturer_photos/0/6/632/standard_microsystems__smsc__sml.jpg)
LAN9420-NU
Manufacturer Part Number
LAN9420-NU
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.LAN9420-NU.pdf
(170 pages)
Specifications of LAN9420-NU
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
128
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LAN9420-NU
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
LAN9420-NU
Manufacturer:
SMSC
Quantity:
20 000
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Revision 1.4 (12-17-08)
4.2.5
30:28
26:24
22:20
18:16
15:11
BITS
31
27
23
19
RESERVED
LED[3:1] enable (LEDx_EN)
A ’1’ sets the associated pin as an LED output. When cleared low, the pin
functions as a GPIO signal. Bits are assigned as follows:
LED1/GPIO0 - bit 28
LED2/GPIO1 - bit 29
LED3/GPIO2 - bit 30
RESERVED
GPIO Interrupt Polarity 0-2 (GPIO_INT_POL)
When set high, a high logic level on the corresponding GPIO pin will set
the corresponding INT_STS register bit. When cleared low, a low logic level
on the corresponding GPIO pin will set the corresponding INT_STS register
bit.
GPIO interrupts must also be enabled in GPIOx_INT_EN in the INT_EN
register. Bits are assigned as follows:
GPIO0 - bit 24
GPIO1 - bit 25
GPIO2 - bit 26
Note:
RESERVED
EEPROM Enable (EEPR_EN)
The value of this field determines the function of the external EEDIO and
EECLK.
Please refer to
the EEPROM Enable bit function definitions.
Note:
RESERVED
GPIO Buffer Type 0-2 (GPIOBUFn)
When set, the output buffer for the corresponding GPIO signal is configured
as a push/pull driver. When cleared, the corresponding GPIO set configured
as an open-drain driver. Bits are assigned as follows:
GPIO0 – bit 16
GPIO1 – bit 17
GPIO2 – bit 18
RESERVED
General Purpose Input/Output Configuration Register (GPIO_CFG)
This register configures the GPIO and LED functions.
Offset:
GPIO inputs must be active for greater than 80nS to be
recognized as interrupt inputs.
The Host must not change the function of the EEDIO and EECLK
pins when an EEPROM read or write cycle is in progress. Do not
use reserved setting.
Table 4.3, “EEPROM Enable Bit Definitions,” on page 93
DESCRIPTION
00D0h
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
DATASHEET
92
Size:
32 bits
for
TYPE
SMSC LAN9420/LAN9420i
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
DEFAULT
000b
000b
000b
000b
Datasheet
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