LAN9420-NU Standard Microsystems (SMSC), LAN9420-NU Datasheet - Page 81

• Manufacturer Part Number: LAN9420-NU
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9420-NU

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i
3.7.6.1
3.7.7
Two control bits are implemented in the PMT_CTRL SCSR: Wake-on-LAN enable (WOL_EN) and
Energy Detect enable (ED_EN). Depending on the state of these control bits, the logic will generate
an internal wake event interrupt when the MAC detects a wakeup event (Wakeup Frame or Magic
Packet), or a PHY interrupt is asserted (energy detect). Two
in the SCSR space. These bits are set depending on the corresponding wake event. (See
4.2.9, "Power Management Control Register (PMT_CTRL)," on page 97
Wakeup Frame detection must be enabled in the MAC before detection can occur. Likewise, the
energy detect interrupt must be enabled in the PHY before this interrupt can be used as a wake event.
If LAN9420/LAN9420i is properly configured, the internal wake event interrupt will cause the assertion
of the nPME signal on detection of a wake event.
When the device is in the D0
interrupt (nINT). Upon detection of the wake event, the wake logic sets the
(WAKE_INT)
will cause the assertion of nINT.
Enabling Wakeup Frame Wake Events
The Host system must perform the following steps to enable LAN9420/LAN9420i to assert a PCI wake
event (nPME) on detection of a Wakeup frame.
1. All transmit and receive operations must be halted:
a. All pending Ethernet TX and RX operations must be completed, and then the DMA controller and
b. The software application must wait for all pending DMA transactions to complete. Upon completion,
2. The MAC must be configured to detect the desired wake event. This process is explained in
3. Bit 1 of the Wakeup Status (WUPS[1]) in the
4. Set the
5. Set the
6. To place the device in the D3 state, set the
On detection of an enabled wakeup frame, the device will assert the nPME signal. The nPME signal
will remain asserted until the
cleared by the Host.
Note: If waking from a reduced-power state causes the assertion of a device reset, bit 4 of the
Enabling Link Status Change (Energy Detect) Wake Events
The Host system must perform the following steps to enable LAN9420/LAN9420i to assert a PCI wake
event (nPME) on detection of an Ethernet link status change.
1. All transmit and receive operations must be halted:
a. All pending Ethernet TX and RX operations must be completed, and then the DMA controller and
MAC must be halted.
no further transactions are permitted.
Section 3.5.4, "Wakeup Frame Detection," on page
must be cleared since a set bit will cause the immediate assertion of wake event when WOL_EN
is set. The WUPS[1] bit will not clear if the internal MAC wakeup event is asserted.
(PMT_CTRL).
(PCI_PMCSR). Note that PME_EN must be set before entering the D3 state. If this bit is not set,
the internal PHY will be reset and placed in the General Power-Down state and the device will not
be able to detect wakeup frames.
Power Management Control and Status Register (PCI_PMCSR)
enter D3
page
MAC must be halted.
Management Control Register (PMT_CTRL)
77.
Wake-On-Lan Wakeup Enable (WOL_EN)
PME Enable (PME_EN)
HOT
status bit in the
. Device behavior in this state is described in
PME Enable (PME_EN)
Interrupt Status Register
A
state, wake event detection can also trigger the assertion of a PCI
DATASHEET
bit in the
81
Power Management State (PM_STATE)
PCI Power Management Control and Status Register
Power Management Control Register (PMT_CTRL)
register (WUPS[1]) will be cleared.
and/or the
(INT_STS). If so enabled, setting this status bit
bit in the
57.
Wakeup Status (WUPS)
Section 3.7.4.4, "The D3HOT State," on
Power Management Control Register
PME Status (PME_STATUS)
to 11b (‘D3’ state). The device will
for further information)
Wake Event Interrupt
Revision 1.4 (12-17-08)
are implemented
field of the
Section
bits are
Power
PCI