S19233PBIFB Applied Micro Circuits Corporation, S19233PBIFB Datasheet

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S19233PBIFB

Manufacturer Part Number
S19233PBIFB
Description
Manufacturer
Applied Micro Circuits Corporation
Datasheet

Specifications of S19233PBIFB

Operating Supply Voltage (typ)
1.8/3.3V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
FEATURES
Figure 1. System Block Diagram
AMCC Confidential and Proprietary
S19233
10 G Ethernet/Fibre Channel/SONET/SDH Dual CDR
Complies with ITU-T specifications, 50 mUI
max. jitter generation (50 KHz - 80 MHz)
Complies with XFP MSA Specifications
25 mUI
CML serial input sensitivity at 5 mV
Dual CDR - 9.95 to 11.32 Gbps operation
Superior Crosstalk Isolation
Electronic Dispersion Compensation (EDC)
Optimized for 0 to 100 Km SMF with 2 dB dis-
persion penalty
Low power EDC ideal for Power Level 2 XFP
modules
Suitable for low Optical Signal to Noise Ratio
(OSNR) environments
Automatic Threshold Adjust
External threshold & Phase Adjust
AGC embedded equalizer
LOS Function - Compliant to GR-253
Integrated equalizer that support over 24” FR-4
on Transmitter Electrical Side
Transmitter (Optical Side) - CDR
Lock detect indication
740 mW Typical Power
-40 to 85°C operation
CMOS 0.13 Micron Technology
1.8 and 3.3 Volt Power Supply
6 mm x 6 mm PBGA package with RoHS com-
pliant lead free option
ESD - 1500 V, 1000 V High Speed Inputs
S19235/37
S19250/52
AMCC
pp
Jitter Generation
XFI
10 Gbps Line Card
Dual CDR
S19233
AMCC
pp
Diff.
pp
XFP Module
APPLICATIONS
GENERAL DESCRIPTION
The S19233 is a fully integrated low power dual CDR
device with Electronic Dispersion Compensation
(EDC). It is suitable for use in 10 GbE/10G FC/
SONET/SDH PMD modules, such as the XFP MSA
modules. This device can be used to compensate
channel impairments caused by either single mode
fiber up to 100 km or FR-4 copper medium over 24”.
Integrated in this device on the receive optical side, an
AGC amplifier with offset cancellation circuitry, EDC/
Equalization with control circuitry, and CDR. On the
transmit electrical side the S19233 also has an equal-
ization circuit, and CDR that reshapes the data after
up to 24" of transmission over copper on FR-4 PWB
material. The low-jitter CML interfaces guarantees
compliance with the bit error rate requirements of the
Telcordia and ITU-T standards. The S19233 is pack-
aged in a 6 mm by 6 mm PBGA, offering designers a
small package outline.
Value Proposition - Design multiple XFP modules
ranging from 2 km to 120 km link with one footprint.
The S19233 is pin and software compatible to the
EDC based 10G Dual CDR S19256.
S19256: 2 km-40 km;
S19233: 40 km-120 km
TOSA
ROSA
10 G Fibre Channel and Ethernet Designs
10 GbE with FEC
10 G SONET/SDH/FEC Designs
SONET/SDH Test Equipment
SONET/SDH/FEC DWDM Equipment
XFP MSA Modules
OC-192/10GE/10FC
Revision 5.00 – March 16, 2007
Part Number S19233
Data Sheet
1

Related parts for S19233PBIFB

S19233PBIFB Summary of contents

Page 1

S19233 10 G Ethernet/Fibre Channel/SONET/SDH Dual CDR FEATURES • Complies with ITU-T specifications, 50 mUI max. jitter generation (50 KHz - 80 MHz) • Complies with XFP MSA Specifications • 25 mUI Jitter Generation pp • CML serial input sensitivity ...

Page 2

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR FEATURES .............................................................................................................................................................. 1 APPLICATIONS ...................................................................................................................................................... 1 GENERAL DESCRIPTION ...................................................................................................................................... 1 TABLE OF CONTENTS .......................................................................................................................................... 2 LIST OF FIGURES .................................................................................................................................................. 4 LIST OF TABLES .................................................................................................................................................... 5 S19233 OVERVIEW ................................................................................................................................................ 6 POWER UP SEQUENCE ...

Page 3

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR SONET Jitter Generation ................................................................................................................................. 15 Sinusoidal Jitter ............................................................................................................................................... 15 Test Pattern ..................................................................................................................................................... 15 PIN ASSIGNMENTS AND DESCRIPTIONS ........................................................................................................ 18 I2C SERIAL CONTROL INTERFACE REGISTER MAP SUMMARY ................................................................... 20 S19233 PINOUT (TOP VIEW) ...

Page 4

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR Figure 1. System Block Diagram ............................................................................................................................. 1 Figure 2. S19233 Dual CDR Block Diagram ............................................................................................................ 7 Figure 3. Two Wire Slave Address ........................................................................................................................ 13 Figure 4. SONET STS-192 Jitter Tolerance Mask ................................................................................................. ...

Page 5

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR Table 1. Standard Compliance List .......................................................................................................................... 6 Table 2. AMCC Suggested Interface Devices ......................................................................................................... 6 Table 3. Receive Squelch Control ........................................................................................................................... 9 Table 4. Transmit Squelch Control ........................................................................................................................ 11 Table 5. Reference ...

Page 6

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR S19233 OVERVIEW The S19233 can be used to implement the front end of SONET/SDH/FEC/10GbE/FC/G.709 equipment which consists primarily of the serial transmit interface and the serial receive interface. The system timing circuitry ...

Page 7

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR Figure 2. S19233 Dual CDR Block Diagram AMCC Confidential and Proprietary Revision 5.00 – March 16, 2007 Data Sheet 7 ...

Page 8

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR RECEIVE OPTICAL SIDE – DESCRIPTION The receive side of the S19233 dual CDR device pro- vides an important EDC function to compensate chromatic dispersion for 10 Gigabit Ethernet/10 G Fibre Channel/SONET STS-192 ...

Page 9

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR Receiver Output Polarity Invert The output data polarity swap is implemented for the ease of design. This adds routing flexibility for either ...

Page 10

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR an LOS condition the PLL will lock to reference until the LOS condition is de-asserted. LOS pin is not con- figured as an open drain or open collector output. The signal detect ...

Page 11

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR Transmit Output Polarity Invert The output data polarity swap is implemented for the ease of design. This adds routing flexibility for either ...

Page 12

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR Reference Clock (REFCLKP/N) – External Pin The Reference Clock (REFCLKP/N) pins are Differen- tial CML 155.52 MHz to 177 MHz input used to establish the initial operating frequency of the clock recovery ...

Page 13

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR I2C BUS and Address Register ® S19233 uses a simple bi-directional two-wire bus for efficient inter-IC control. All register controlled features and functions are programmed via the I 11summarizes the register map ...

Page 14

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR SONET AND ETHERNET JITTER CRITERIA SONET Jitter Transfer The following jitter transfer requirement applies to STS- 192 interfaces as defined in GR-253-Core. For STS- 192 interfaces, the jitter transfer function shall meet ...

Page 15

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR SONET Jitter Generation The following jitter generation requirement applies to STS-192 interfaces as defined in GR-253-CORE. According to GR-253-CORE, jitter generation shall not exceed 0.10 UI for STS-192 interfaces when PP measured ...

Page 16

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR Figure 5. Input Jitter for Receiver Test - -10 10 -12 10 Figure 6. Applied Sinusoidal Jitter - 10GbE 5 UI Applied Sinusoidal Jitter peak-to-peak Amplitude (UI) (Log Scale) ...

Page 17

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR Table 6. Applied Sinusoidal Jitter Frequency Range f < 40 kHz 40 kHz < f < 4 MHz 4 MHz < f < Figure 7. Scrambler and Descrambler S0 S1 ...

Page 18

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR PIN ASSIGNMENTS AND DESCRIPTIONS Table 9. Signals Pin Assignments and Descriptions Pin Name Level I/O TXDATINP High I TXDATINN Speed Diff CML TXCAP1 Analog I TXCAP2 TXLOCK 3 LVTTL TXDATOUTP ...

Page 19

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR Table 9. Signals Pin Assignments and Descriptions (Continued) Pin Name Level I/O PD/RSTB LVCMOS I pull-down REFCLKP LVPECL I REFCLKN SDA I2C I/O SCL ® I BUS SCANMODE LVTTL I Pull- down ...

Page 20

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR I2C SERIAL CONTROL INTERFACE REGISTER MAP SUMMARY Table 11 below contains the register map summary for the S19233. For detailed register descriptions, please consult the S19233 - Program- mer’s Reference Manual: PRM2001. ...

Page 21

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR Table 11. Register Map Summary Default Address Bit a (hex) Field Value 0x08 - 7:0 RESERVED 0x09 0101 0001 6:0 DEVICE_ADDR 0x0A - 7:0 RESERVED 0x0B 00-- ---- 7 RXCOREPD 6 TXCOREPD ...

Page 22

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR Table 11. Register Map Summary Default Address Bit a (hex) Field Value 0x71 1100 0000 6:5 TX_PA_STEP_CNTL 4:0 TX_EQ_CNTL_LINK_ OPT2 0x72 1010 0011 4:0 TX_EQ_CNLT_LINK_ OPT1 0x73 - - 7:0 RESERVED - ...

Page 23

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR S19233 PINOUT (TOP VIEW) Figure 8. S19233 Pinout (Top View RXDATINP RXDATINN A VSS VDD_PA_RX B AVDD_RX RXCTAP C RXCAP1 VSS D RXCAP2 VSS E AVDD_RX VDD_RX F VSS RXDATOUTN ...

Page 24

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR S19233 – 49 PBGA PACKAGE MECHANICAL DRAWING Figure 9. S19233 – 49 PBGA Package Mechanical Drawing PACKAGE MATERIAL NOTE: Standard Package: Ball Composition - 63/37 Sn/Pb. Green / RoHS Compliant Package: Ball ...

Page 25

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR S19233 – 49 PBGA PACKAGE MARKING DRAWING Figure 10. S19233 – 49 PBGA Package Marking Drawing (Top View) NOTES (Unless Otherwise Specified): Dot Represents PIN 1 (A01) Designator 1 Engineering Sample designator ...

Page 26

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR PERFORMANCE SPECIFICATIONS High-speed/low noise design practices must be implemented to meet the following performance specifications. Consult AMCC’s Applications Engineering Department for recommendations regarding your specific application: support@amcc.com. Table 13. Performance Specifications Parameter ...

Page 27

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR Table 13. Performance Specifications (Continued) Parameter SDD11 (Figure 12, Point B) Differential input Return Loss SCC11 (Figure 12, Point B) Common Mode Input Return Loss SCD11 (Figure 12, Point B) Common Mode ...

Page 28

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR Table 13. Performance Specifications (Continued) Parameter Transmitter Jitter Generation J for Tele- gen com (Figure 12, Point E, 50K-80M band Jit- ter) Transmitter Jitter Tolerance J for Datacom tol (Figure 12, Point ...

Page 29

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR Table 13. Performance Specifications (Continued) Parameter Receiver Output Jitter for Datacom (Figure 12, Point C, Broadband Jitter) Receiver Jitter Transfer Bandwidth for Data- com (Figure 12, Point C) Receiver Jitter Transfer Bandwidth ...

Page 30

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR Figure 11. 155.52 MHz REFCLK Phase Noise -60 -80 -100 -120 -140 -160 10 1, Figure 12. S19233 with XFP System Performance Points 30 pin Connector B A AMCC S19235/ ...

Page 31

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR ELECTRICAL CHARACTERISTICS Table 14. Absolute Maximum Stress Ratings The following are the absolute maximum stress ratings for the S19233 device. Stresses beyond those listed may cause permanent damage to the device. Absolute ...

Page 32

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR Table 16. Serial I/O Interface Specifications Parameter Description Serial Output Differential Voltage V Default - Low swing ODIFF High swing t & t Rise and Fall Times f (20-80 Differential ...

Page 33

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR 2 Table 18 Input/Output Characteristics Parameter Description V Input High Voltage IH V Input Low Voltage IL I Input Leakage Current IN V Output High Voltage OH V Output Low ...

Page 34

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR EXTERNAL LOOP FILTER COMPONENTS Table 19. Transmit and Receive External Loop Filter Components, See Figure 14 CSU_REFCLK Reference Designator 155.52 MHz REFCLK R 155.52 MHz REFCLK R Figure 14. External Loop Filter ...

Page 35

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR RECOMMENDED TERMINATIONS Figure 16. S19233 Differential CML Output to +5 V/+3.3 V LVPECL Input AC Coupled Termination +1.8 V S19233 TXDOUTP/N Figure 17 Differential PECL Driver to S19233 Differential CML ...

Page 36

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR Figure 19. + 1.2 V Differential CML Driver to S19233 Differential CML Input AC Coupled Termination + 1.2 V Example: S19235/37 CML Output 36 Revision 5.00 – March 16, 2007 Internally Biased ...

Page 37

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR DOCUMENT REVISION HISTORY Revision Date 5.00 3/16/07 • Page 1, Changed 650 mW to 740 mW for Typical Power. • Page 6, Included Power Up Sequence paragraph • Page 13, Updated default ...

Page 38

S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR DOCUMENT REVISION HISTORY (CONTINUED) Revision Date 2.00 04/29/05 • Page 1, Updated feature list • Page 14-17, Updated SONET and Ethernet Jitter sections • Page 20, Update Table 11, Register Map Summary ...

Page 39

... S19233 – Ethernet/Fibre Channel/SONET/SDH Dual CDR ORDERING INFORMATION Device Code S19233PBIFB S19233 - 10 G Ethernet/Fibre Channel/SONET/SDH Dual CDR Industrial Temp, Standard Package S19233PRIB S19233 - 10 G Ethernet/Fibre Channel/SONET/SDH Dual CDR Industrial Temp, RoHS Compliant Package S19233 XX Phone: (858) 450-9333 — (800) 755-2622 — Fax: (858) 450-9885 ...

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