S19233PBIFB Applied Micro Circuits Corporation, S19233PBIFB Datasheet - Page 12

• Manufacturer Part Number: S19233PBIFB
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S19233PBIFB

• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

S19233 – 10 G Ethernet/Fibre Channel/SONET/SDH
Dual CDR
Reference Clock (REFCLKP/N) – External Pin
The Reference Clock (REFCLKP/N) pins are Differen-
tial CML 155.52 MHz to 177 MHz input used to
establish the initial operating frequency of the clock
recovery Phase Lock Loop (PLL) and is also used in
the absence of data to maintain PLL lock. Table 5
summarizes the REFCLK rates used in typical applica-
Table 5. Reference Frequency for the Clock Recovery Unit
PD – External Pin
Powerdown/Reset pin. This is a dual purpose pin.
Active high. Default low, when high, power downs the
Transmitter and Receiver. The l2C interface and reset
generation logic is functional during power-down with
REFCLK supplied. The falling edge initiates a com-
plete reset of TX/RX including 2-wire serial interface.
The reset function asynchronously resets the device.
Electrical Diagnostic Loopback Enable (XLEB) –
I
The XLEB is an active low input that selects the diag-
nostic loopback mode. In this mode, the Transmitter
Data (TXD) is routed internally to the receive side. The
12
2
STS-192, Reed Soloman
STS-192, Reed Soloman
Reed Soloman - 255/238
Reed Soloman - 255/237
C Register
66B Encoded - 255/238
66B Encoded - 255/237
10 Gigabit Ethernet 64/
10 Gigabit Ethernet 64/
10 Gigabit Ethernet 64/
10 G Fibre Channel,
10 G Fibre Channel,
10 Gigabit Ethernet
10 G Fibre Channel
Error Correcting
STS-192, 0 bytes
66B Encoded
Capability
- 255/238
- 255/237
Synchronization Byte (FSB)
Expansion Due to Code
Percentage Bandwidth
Words and Frame
3.125% increase
7.14% increase
7.59% increase
7.14% increase
7.59% increase
7.14% increase
7.59% increase
0% increase
0% increase
0% increase
Increased Receive
10.51875 Gbps
tions. This input is internally biased and terminated
100
ally, Table 5. shows the corresponding RX and TX
register configured VCO selections for the frequency
of operation. See S19233 Programming Manual for
additional information on RX and TX VCO selection.
serial data is recovered by the receive CDR then send
back out the electrical side through pin RXDATOUTP/
N. This mode is accessible through the I
register.
Optical Side Line Loopback Enable (OLEB) – I
Register
This active low input selects line loopback mode. In
this mode, the Receiver Data (RXD) from the receive
side is routed internally to the transmit side. The serial
data is recovered by the transmit CDR then send back
out the optical side through pin TXDATOUTP/N. This
mode is accessible through the I2C BUS
10.3125 Gbps
11.0491 Gbps
11.0957 Gbps
10.709 Gbps
10.000 Gbps
9.953 Gbps
10.66 Gbps
(SERDATI)
Frequency
11.27 Gbps
11.32 Gbps
Data Input
Ω
line-to-line and must be AC coupled. Addition-
172.642 MHz
176.095 MHz
155.52 MHz
166.63 MHz
167.33 MHz
156.25 MHz
161.13 MHz
173.37 MHz
164.35 MHz
176.84 MHz
Frequency
(REFCLK)
Required
Revision 5.00 – March 16, 2007
AMCC Confidential and Proprietary
RX_VCO_SEL[1:0]/
Data Sheet
TX_VCO_SEL[1:0]
®
register.
01
10
10
01
01
11
11
10
11
11
2
C bus
2
C