S19233PBIFB Applied Micro Circuits Corporation, S19233PBIFB Datasheet - Page 4

• Manufacturer Part Number: S19233PBIFB
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S19233PBIFB

• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Revision 5.00 – March 16, 2007
S19233 – 10 G Ethernet/Fibre Channel/SONET/SDH
Data Sheet
Dual CDR
LIST OF FIGURES
Figure 1. System Block Diagram ............................................................................................................................. 1
Figure 2. S19233 Dual CDR Block Diagram ............................................................................................................ 7
Figure 3. Two Wire Slave Address ........................................................................................................................ 13
Figure 4. SONET STS-192 Jitter Tolerance Mask ................................................................................................. 14
Figure 5. Input Jitter for Receiver Test ................................................................................................................... 16
Figure 6. Applied Sinusoidal Jitter - 10GbE ........................................................................................................... 16
Figure 7. Scrambler and Descrambler ................................................................................................................... 17
Figure 8. S19233 Pinout (Top View) ...................................................................................................................... 23
Figure 9. S19233 – 49 PBGA Package Mechanical Drawing ................................................................................ 24
Figure 10. S19233 – 49 PBGA Package Marking Drawing (Top View) ................................................................. 25
Figure 11. 155.52 MHz REFCLK Phase Noise ...................................................................................................... 30
Figure 12. S19233 with XFP System Performance Points ..................................................................................... 30
2
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Figure 13. I
C BUS
Timing Diagram .................................................................................................................... 33
Figure 14. External Loop Filter Components ......................................................................................................... 34
Figure 15. Differential Voltage Measurement ........................................................................................................ 34
Figure 16. S19233 Differential CML Output to +5 V/+3.3 V LVPECL Input AC Coupled Termination ................... 35
Figure 17. +5 V Differential PECL Driver to S19233 Differential CML Input AC Coupled Termination .................. 35
Figure 18. +5 V/+3.3 V Differential PECL Driver to S19233 CML Reference Clock Input AC Coupled Termination ....35
Figure 19. + 1.2 V Differential CML Driver to S19233 Differential CML Input AC Coupled Termination ............... 36
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