PEB4265VV12NT Infineon Technologies, PEB4265VV12NT Datasheet - Page 67

• Manufacturer Part Number: PEB4265VV12NT
• Manufacturer: Infineon Technologies

Specifications of PEB4265VV12NT

• On-hook Transmission: Yes
• Polarity Reversal: Yes
• On-chip Ring Relay Driver: Yes
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 22
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Preliminary
DuSLIC FSK Generation
Different countries use different standards to send Caller ID information. The DuSLIC
chip set is compatible with the widely used standards Bellcore GR-30-CORE, British
Telecom (BT) SIN227, SIN242 or the UK Cable Communications Association (CCA)
specification TW/P&E/312. Continuous phase binary frequency shift keying (FSK)
modulation is used for coding which is compatible with BELL 202 (see
ITU-T V.23, the most common standards. SLICOFI-2 can be easily adapted to these
requirements by programming via the microcontroller interface. Coefficient sets are
provided for the most common standards.
Table 8
Characteristic
Mark (Logic 1)
Space (Logic 0)
Modulation
Transmission rate
Data format
The Caller ID data of the calling party can be transferred via the microcontroller interface
into a SLICOFI-2 buffer register. The SLICOFI-2 will start sending the FSK signal when
the CIS-EN bit is set and the CID-data buffer is filled up to CIS-BRS plus 1 byte. The data
transfer into the buffer register is handled by a SLICOFI-2 interrupt signal. Caller data is
transferred from the buffer via the interface pins to the SLIC-E/-E2/-P and fed to the Tip
and Ring wires. The Caller ID data bytes from CID-data buffer are sent LSB first.
DuSLIC offers two different levels of framing:
• A basic low-level framing mode
• A high level framing mode
The example below shows signaling of CID on-hook data transmission in accordance
with Bellcore specifications. The Caller ID information applied on Tip and Ring is sent
during the period between the first and second ring burst.
Data Sheet
All the data necessary to implement the FSK data stream – including channel
seizure, mark sequence and framing for the data packet or checksum – has to be
configured by firmware. SLICOFI-2 transmits the data stream in the same order in
which the data is written to the buffer register.
The number of channel seizure and mark bits can be programmed and are
automatically sent by the DuSLIC. Only the data packet information has to be written
into the CID buffer. Start and Stop bits are automatically inserted by the SLICOFI-2.
FSK Modulation Characteristics
ITU-T V.23
1300 ± 3 Hz
2100 ± 3 Hz
67
Serial binary asynchronous
1200 ± 6 baud
FSK
Bell 202
1200 ± 3 Hz
2200 ± 3 Hz
Functional Description
Table
2000-07-14
DuSLIC
8) and